Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	32309	1		T1	8		T2	4		T10	8
auto[1]	74	1		T31	6		T199	13		T29	1
auto[2]	45	1		T25	6		T187	1		T221	2
auto[3]	178	1		T25	7		T31	2		T32	9

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	8156	1		T1	2		T2	1		T10	2
evic_idx[1]	8155	1		T1	2		T2	1		T10	2
evic_idx[2]	8150	1		T1	2		T2	1		T10	2
evic_idx[3]	8145	1		T1	2		T2	1		T10	2

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	31613	1		T2	4		T57	576		T25	13
evic_op[2]	343	1		T80	12		T125	1		T129	8

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7848	1		T2	1		T57	144		T97	177
evic_idx[0]	evic_op[1]	auto[1]	17	1		T31	3		T199	3		T198	3
evic_idx[0]	evic_op[1]	auto[2]	3	1		T25	2		T401	1		-	-
evic_idx[0]	evic_op[1]	auto[3]	40	1		T25	2		T31	1		T32	3
evic_idx[0]	evic_op[2]	auto[0]	69	1		T80	3		T129	2		T73	1
evic_idx[0]	evic_op[2]	auto[1]	2	1		T29	1		T402	1		-	-
evic_idx[0]	evic_op[2]	auto[2]	4	1		T187	1		T221	1		T403	1
evic_idx[0]	evic_op[2]	auto[3]	9	1		T39	1		T326	1		T404	1
evic_idx[1]	evic_op[1]	auto[0]	7849	1		T2	1		T57	144		T97	177
evic_idx[1]	evic_op[1]	auto[1]	17	1		T31	1		T199	5		T405	6
evic_idx[1]	evic_op[1]	auto[2]	5	1		T25	2		T401	3		-	-
evic_idx[1]	evic_op[1]	auto[3]	34	1		T31	1		T32	2		T138	1
evic_idx[1]	evic_op[2]	auto[0]	72	1		T80	3		T129	2		T73	1
evic_idx[1]	evic_op[2]	auto[1]	5	1		T406	1		T403	1		T407	1
evic_idx[1]	evic_op[2]	auto[2]	3	1		T408	1		T409	1		T410	1
evic_idx[1]	evic_op[2]	auto[3]	8	1		T185	1		T411	1		T293	1
evic_idx[2]	evic_op[1]	auto[0]	7851	1		T2	1		T57	144		T97	177
evic_idx[2]	evic_op[1]	auto[1]	15	1		T31	1		T199	3		T405	4
evic_idx[2]	evic_op[1]	auto[2]	4	1		T25	1		T401	3		-	-
evic_idx[2]	evic_op[1]	auto[3]	32	1		T25	3		T32	2		T138	1
evic_idx[2]	evic_op[2]	auto[0]	68	1		T80	3		T129	2		T73	1
evic_idx[2]	evic_op[2]	auto[1]	1	1		T412	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[2]	3	1		T221	1		T403	1		T409	1
evic_idx[2]	evic_op[2]	auto[3]	14	1		T125	1		T30	1		T413	1
evic_idx[3]	evic_op[1]	auto[0]	7850	1		T2	1		T57	144		T97	177
evic_idx[3]	evic_op[1]	auto[1]	13	1		T31	1		T199	2		T198	2
evic_idx[3]	evic_op[1]	auto[2]	3	1		T25	1		T401	2		-	-
evic_idx[3]	evic_op[1]	auto[3]	32	1		T25	2		T32	2		T401	1
evic_idx[3]	evic_op[2]	auto[0]	68	1		T80	3		T129	2		T73	1
evic_idx[3]	evic_op[2]	auto[1]	4	1		T408	1		T414	1		T415	1
evic_idx[3]	evic_op[2]	auto[2]	4	1		T413	1		T408	2		T410	1
evic_idx[3]	evic_op[2]	auto[3]	9	1		T416	1		T417	1		T418	1