Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	51662	1		T200	1774		T341	14858		T342	15416
rd_lvl[2]	62613	1		T287	1180		T200	1055		T341	10854
rd_lvl[3]	13658	1		T343	989		T287	2135		T200	423
rd_lvl[4]	22775	1		T26	5841		T343	1016		T287	444
rd_lvl[5]	9808	1		T26	559		T195	820		T344	867
rd_lvl[6]	4585	1		T195	312		T344	190		T343	83
rd_lvl[7]	5110	1		T195	57		T345	1899		T343	23
rd_lvl[8]	15019	1		T24	782		T195	57		T345	1569
rd_lvl[9]	4743	1		T27	347		T24	159		T287	990
rd_lvl[10]	4051	1		T27	1395		T295	1214		T327	15
rd_lvl[11]	3885	1		T24	97		T195	59		T208	611
rd_lvl[12]	4238	1		T208	1009		T37	237		T327	1
rd_lvl[13]	2966	1		T28	491		T343	69		T346	151
rd_lvl[14]	11158	1		T28	1275		T36	239		T37	80
rd_lvl[15]	3907	1		T36	540		T347	513		T348	137