Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	343422	1		T1	2		T2	2		T3	2
all_pins[1]	343422	1		T1	2		T2	2		T3	2
all_pins[2]	343422	1		T1	2		T2	2		T3	2
all_pins[3]	343422	1		T1	2		T2	2		T3	2
all_pins[4]	343422	1		T1	2		T2	2		T3	2
all_pins[5]	343422	1		T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1737043	1		T1	12		T2	12		T3	12
values[0x1]	323489	1		T26	8000		T27	3484		T28	3532
transitions[0x0=>0x1]	293627	1		T26	6400		T27	3484		T28	3532
transitions[0x1=>0x0]	293611	1		T26	6400		T27	3484		T28	3532

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	343263	1		T1	2		T2	2		T3	2
all_pins[0]	values[0x1]	159	1		T268	3		T270	5		T334	3
all_pins[0]	transitions[0x0=>0x1]	75	1		T268	1		T270	1		T334	1
all_pins[0]	transitions[0x1=>0x0]	78	1		T268	1		T269	3		T270	2
all_pins[1]	values[0x0]	343260	1		T1	2		T2	2		T3	2
all_pins[1]	values[0x1]	162	1		T268	3		T269	3		T270	6
all_pins[1]	transitions[0x0=>0x1]	135	1		T268	3		T269	2		T270	5
all_pins[1]	transitions[0x1=>0x0]	1176	1		T36	2		T347	1050		T348	51
all_pins[2]	values[0x0]	342219	1		T1	2		T2	2		T3	2
all_pins[2]	values[0x1]	1203	1		T36	2		T347	1050		T348	51
all_pins[2]	transitions[0x0=>0x1]	42	1		T269	1		T270	1		T334	1
all_pins[2]	transitions[0x1=>0x0]	220375	1		T26	6400		T27	1742		T28	1766
all_pins[3]	values[0x0]	121886	1		T1	2		T2	2		T3	2
all_pins[3]	values[0x1]	221536	1		T26	6400		T27	1742		T28	1766
all_pins[3]	transitions[0x0=>0x1]	192996	1		T26	4800		T27	1742		T28	1766
all_pins[3]	transitions[0x1=>0x0]	71830	1		T27	1742		T28	1766		T22	1611
all_pins[4]	values[0x0]	243052	1		T1	2		T2	2		T3	2
all_pins[4]	values[0x1]	100370	1		T26	1600		T27	1742		T28	1766
all_pins[4]	transitions[0x0=>0x1]	100361	1		T26	1600		T27	1742		T28	1766
all_pins[4]	transitions[0x1=>0x0]	50	1		T270	1		T337	1		T338	2
all_pins[5]	values[0x0]	343363	1		T1	2		T2	2		T3	2
all_pins[5]	values[0x1]	59	1		T270	1		T337	1		T338	2
all_pins[5]	transitions[0x0=>0x1]	18	1		T338	1		T335	1		T339	1
all_pins[5]	transitions[0x1=>0x0]	102	1		T268	2		T270	3		T334	3