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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.32 95.71 94.00 98.31 92.52 98.25 97.28 98.15


Total test records in report: 1261
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T1073 /workspace/coverage/default/3.flash_ctrl_prog_reset.4155055299 Jun 29 07:12:56 PM PDT 24 Jun 29 07:13:11 PM PDT 24 61977000 ps
T1074 /workspace/coverage/default/1.flash_ctrl_disable.1998270628 Jun 29 07:11:11 PM PDT 24 Jun 29 07:11:34 PM PDT 24 39489800 ps
T1075 /workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.2023794822 Jun 29 07:15:54 PM PDT 24 Jun 29 07:16:08 PM PDT 24 26237900 ps
T1076 /workspace/coverage/default/13.flash_ctrl_mp_regions.633557186 Jun 29 07:17:32 PM PDT 24 Jun 29 07:23:19 PM PDT 24 19856867300 ps
T1077 /workspace/coverage/default/6.flash_ctrl_fetch_code.1614525386 Jun 29 07:14:43 PM PDT 24 Jun 29 07:15:10 PM PDT 24 588182800 ps
T45 /workspace/coverage/default/1.flash_ctrl_access_after_disable.2584361327 Jun 29 07:11:19 PM PDT 24 Jun 29 07:11:34 PM PDT 24 20969000 ps
T1078 /workspace/coverage/default/3.flash_ctrl_rw_evict.1586152876 Jun 29 07:13:04 PM PDT 24 Jun 29 07:13:35 PM PDT 24 84769500 ps
T1079 /workspace/coverage/default/19.flash_ctrl_smoke.3684241823 Jun 29 07:19:13 PM PDT 24 Jun 29 07:20:53 PM PDT 24 77167800 ps
T1080 /workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.2150292848 Jun 29 07:18:18 PM PDT 24 Jun 29 07:19:12 PM PDT 24 10034947700 ps
T1081 /workspace/coverage/default/4.flash_ctrl_hw_read_seed_err.4226994543 Jun 29 07:14:02 PM PDT 24 Jun 29 07:14:16 PM PDT 24 15630600 ps
T1082 /workspace/coverage/default/39.flash_ctrl_smoke.1917586442 Jun 29 07:21:50 PM PDT 24 Jun 29 07:23:09 PM PDT 24 23720000 ps
T1083 /workspace/coverage/default/67.flash_ctrl_connect.1821872546 Jun 29 07:22:55 PM PDT 24 Jun 29 07:23:12 PM PDT 24 45488500 ps
T1084 /workspace/coverage/default/5.flash_ctrl_lcmgr_intg.3521790864 Jun 29 07:14:33 PM PDT 24 Jun 29 07:14:48 PM PDT 24 15340700 ps
T1085 /workspace/coverage/default/9.flash_ctrl_connect.1842549340 Jun 29 07:16:17 PM PDT 24 Jun 29 07:16:31 PM PDT 24 22418600 ps
T1086 /workspace/coverage/default/5.flash_ctrl_re_evict.2265892330 Jun 29 07:14:26 PM PDT 24 Jun 29 07:15:01 PM PDT 24 57632300 ps
T1087 /workspace/coverage/default/9.flash_ctrl_error_prog_win.2403239043 Jun 29 07:16:02 PM PDT 24 Jun 29 07:33:07 PM PDT 24 414073500 ps
T1088 /workspace/coverage/default/45.flash_ctrl_connect.1942043188 Jun 29 07:22:22 PM PDT 24 Jun 29 07:22:39 PM PDT 24 28452300 ps
T1089 /workspace/coverage/default/15.flash_ctrl_otp_reset.2654938907 Jun 29 07:18:01 PM PDT 24 Jun 29 07:19:55 PM PDT 24 56785200 ps
T1090 /workspace/coverage/default/6.flash_ctrl_intr_rd_slow_flash.1449108050 Jun 29 07:14:57 PM PDT 24 Jun 29 07:17:39 PM PDT 24 5505168100 ps
T1091 /workspace/coverage/default/18.flash_ctrl_mp_regions.532084996 Jun 29 07:18:51 PM PDT 24 Jun 29 07:29:21 PM PDT 24 311021286200 ps
T1092 /workspace/coverage/default/14.flash_ctrl_phy_arb.2447951672 Jun 29 07:17:39 PM PDT 24 Jun 29 07:23:04 PM PDT 24 327916600 ps
T1093 /workspace/coverage/default/30.flash_ctrl_otp_reset.3484874097 Jun 29 07:20:48 PM PDT 24 Jun 29 07:22:39 PM PDT 24 49858000 ps
T1094 /workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.3588803471 Jun 29 07:09:49 PM PDT 24 Jun 29 07:10:13 PM PDT 24 223284900 ps
T1095 /workspace/coverage/default/20.flash_ctrl_alert_test.715461025 Jun 29 07:19:39 PM PDT 24 Jun 29 07:19:53 PM PDT 24 58515300 ps
T1096 /workspace/coverage/default/1.flash_ctrl_read_word_sweep_derr.3968527926 Jun 29 07:10:59 PM PDT 24 Jun 29 07:11:28 PM PDT 24 78183000 ps
T1097 /workspace/coverage/default/18.flash_ctrl_alert_test.1025763853 Jun 29 07:19:13 PM PDT 24 Jun 29 07:19:28 PM PDT 24 75220600 ps
T1098 /workspace/coverage/default/0.flash_ctrl_rw_derr.3098362566 Jun 29 07:09:46 PM PDT 24 Jun 29 07:21:38 PM PDT 24 5148754800 ps
T1099 /workspace/coverage/default/2.flash_ctrl_sw_op.1826039334 Jun 29 07:11:36 PM PDT 24 Jun 29 07:12:04 PM PDT 24 23572100 ps
T1100 /workspace/coverage/default/8.flash_ctrl_invalid_op.3524802327 Jun 29 07:15:35 PM PDT 24 Jun 29 07:17:13 PM PDT 24 4270296300 ps
T1101 /workspace/coverage/default/5.flash_ctrl_sec_info_access.4195679294 Jun 29 07:14:26 PM PDT 24 Jun 29 07:15:45 PM PDT 24 6396613200 ps
T1102 /workspace/coverage/default/11.flash_ctrl_ro.71649602 Jun 29 07:16:49 PM PDT 24 Jun 29 07:19:13 PM PDT 24 574160600 ps
T1103 /workspace/coverage/default/15.flash_ctrl_smoke.3530691320 Jun 29 07:17:56 PM PDT 24 Jun 29 07:20:00 PM PDT 24 43061300 ps
T1104 /workspace/coverage/default/2.flash_ctrl_rw_derr.2902925387 Jun 29 07:11:58 PM PDT 24 Jun 29 07:21:24 PM PDT 24 8223673100 ps
T1105 /workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.3189523026 Jun 29 07:18:35 PM PDT 24 Jun 29 07:19:48 PM PDT 24 10019680600 ps
T1106 /workspace/coverage/default/12.flash_ctrl_hw_rma_reset.3075236377 Jun 29 07:17:05 PM PDT 24 Jun 29 07:37:42 PM PDT 24 290267383100 ps
T1107 /workspace/coverage/default/2.flash_ctrl_read_word_sweep_derr.26693769 Jun 29 07:11:57 PM PDT 24 Jun 29 07:12:26 PM PDT 24 75712300 ps
T1108 /workspace/coverage/default/39.flash_ctrl_connect.3347861129 Jun 29 07:21:56 PM PDT 24 Jun 29 07:22:10 PM PDT 24 23900100 ps
T1109 /workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.117372296 Jun 29 07:12:58 PM PDT 24 Jun 29 07:17:51 PM PDT 24 11206510600 ps
T1110 /workspace/coverage/default/2.flash_ctrl_mp_regions.2891638946 Jun 29 07:11:43 PM PDT 24 Jun 29 07:22:00 PM PDT 24 41984619400 ps
T1111 /workspace/coverage/default/7.flash_ctrl_otp_reset.1548427248 Jun 29 07:15:09 PM PDT 24 Jun 29 07:17:04 PM PDT 24 38859800 ps
T1112 /workspace/coverage/default/6.flash_ctrl_lcmgr_intg.2290681861 Jun 29 07:14:58 PM PDT 24 Jun 29 07:15:12 PM PDT 24 60256000 ps
T1113 /workspace/coverage/default/17.flash_ctrl_sec_info_access.1952229964 Jun 29 07:18:44 PM PDT 24 Jun 29 07:20:04 PM PDT 24 8525846700 ps
T1114 /workspace/coverage/default/17.flash_ctrl_mp_regions.3846579586 Jun 29 07:18:43 PM PDT 24 Jun 29 07:39:06 PM PDT 24 36245214000 ps
T1115 /workspace/coverage/default/23.flash_ctrl_rw_evict_all_en.1124412911 Jun 29 07:19:57 PM PDT 24 Jun 29 07:20:30 PM PDT 24 64112000 ps
T1116 /workspace/coverage/default/9.flash_ctrl_re_evict.547773201 Jun 29 07:16:18 PM PDT 24 Jun 29 07:16:50 PM PDT 24 117959200 ps
T1117 /workspace/coverage/default/15.flash_ctrl_rw.2404110469 Jun 29 07:18:08 PM PDT 24 Jun 29 07:28:48 PM PDT 24 8021013100 ps
T70 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.3517069103 Jun 29 07:24:21 PM PDT 24 Jun 29 07:24:40 PM PDT 24 119458700 ps
T71 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.3199389624 Jun 29 07:23:23 PM PDT 24 Jun 29 07:23:43 PM PDT 24 101695200 ps
T72 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.1392038440 Jun 29 07:23:50 PM PDT 24 Jun 29 07:24:11 PM PDT 24 73814000 ps
T268 /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.1776591356 Jun 29 07:24:31 PM PDT 24 Jun 29 07:24:46 PM PDT 24 55640900 ps
T99 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.490878748 Jun 29 07:23:43 PM PDT 24 Jun 29 07:24:01 PM PDT 24 208874800 ps
T1118 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.204711987 Jun 29 07:23:33 PM PDT 24 Jun 29 07:23:47 PM PDT 24 52174800 ps
T1119 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1591898268 Jun 29 07:24:05 PM PDT 24 Jun 29 07:24:20 PM PDT 24 12250600 ps
T209 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3661223256 Jun 29 07:23:34 PM PDT 24 Jun 29 07:23:54 PM PDT 24 48257900 ps
T1120 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.149919308 Jun 29 07:23:05 PM PDT 24 Jun 29 07:23:19 PM PDT 24 38125600 ps
T210 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.4228264237 Jun 29 07:24:10 PM PDT 24 Jun 29 07:24:30 PM PDT 24 45265700 ps
T211 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.1115214483 Jun 29 07:23:08 PM PDT 24 Jun 29 07:23:28 PM PDT 24 74011300 ps
T255 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3182383584 Jun 29 07:23:47 PM PDT 24 Jun 29 07:24:02 PM PDT 24 68468100 ps
T263 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.3611711720 Jun 29 07:23:05 PM PDT 24 Jun 29 07:23:46 PM PDT 24 2659492600 ps
T269 /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.389487804 Jun 29 07:23:48 PM PDT 24 Jun 29 07:24:04 PM PDT 24 53374000 ps
T256 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1980416725 Jun 29 07:23:48 PM PDT 24 Jun 29 07:24:07 PM PDT 24 144577900 ps
T257 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.717089701 Jun 29 07:23:22 PM PDT 24 Jun 29 07:23:38 PM PDT 24 174802900 ps
T270 /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.3531093907 Jun 29 07:23:25 PM PDT 24 Jun 29 07:23:39 PM PDT 24 35083600 ps
T265 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.586909064 Jun 29 07:23:05 PM PDT 24 Jun 29 07:23:22 PM PDT 24 62981200 ps
T212 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.265091832 Jun 29 07:23:31 PM PDT 24 Jun 29 07:39:36 PM PDT 24 3445454400 ps
T334 /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.4142121092 Jun 29 07:23:57 PM PDT 24 Jun 29 07:24:12 PM PDT 24 100971200 ps
T242 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.2836279556 Jun 29 07:23:50 PM PDT 24 Jun 29 07:24:09 PM PDT 24 75679900 ps
T264 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.802570881 Jun 29 07:23:13 PM PDT 24 Jun 29 07:24:31 PM PDT 24 9489507100 ps
T1121 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.295434579 Jun 29 07:23:41 PM PDT 24 Jun 29 07:23:57 PM PDT 24 40103600 ps
T337 /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.562407322 Jun 29 07:24:32 PM PDT 24 Jun 29 07:24:46 PM PDT 24 66016400 ps
T1122 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.4240676587 Jun 29 07:23:49 PM PDT 24 Jun 29 07:24:08 PM PDT 24 47374800 ps
T245 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.3586417516 Jun 29 07:23:14 PM PDT 24 Jun 29 07:38:12 PM PDT 24 721950100 ps
T338 /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.1546338474 Jun 29 07:23:49 PM PDT 24 Jun 29 07:24:04 PM PDT 24 52933600 ps
T243 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.870115120 Jun 29 07:24:12 PM PDT 24 Jun 29 07:24:33 PM PDT 24 61424400 ps
T1123 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.2821109558 Jun 29 07:23:43 PM PDT 24 Jun 29 07:23:59 PM PDT 24 41262600 ps
T1124 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.3258834554 Jun 29 07:23:14 PM PDT 24 Jun 29 07:24:01 PM PDT 24 79521300 ps
T1125 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.2606589545 Jun 29 07:24:14 PM PDT 24 Jun 29 07:24:32 PM PDT 24 17430400 ps
T1126 /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.345155997 Jun 29 07:24:29 PM PDT 24 Jun 29 07:24:44 PM PDT 24 19505000 ps
T1127 /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.3933080214 Jun 29 07:23:48 PM PDT 24 Jun 29 07:24:07 PM PDT 24 228887800 ps
T246 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.180412280 Jun 29 07:23:32 PM PDT 24 Jun 29 07:23:47 PM PDT 24 26996600 ps
T335 /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.632169418 Jun 29 07:24:28 PM PDT 24 Jun 29 07:24:43 PM PDT 24 50032600 ps
T1128 /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3961499924 Jun 29 07:24:31 PM PDT 24 Jun 29 07:24:46 PM PDT 24 48659400 ps
T244 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1692768832 Jun 29 07:23:32 PM PDT 24 Jun 29 07:23:50 PM PDT 24 25947000 ps
T1129 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.3582866687 Jun 29 07:23:24 PM PDT 24 Jun 29 07:23:38 PM PDT 24 11457100 ps
T273 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3813300315 Jun 29 07:23:57 PM PDT 24 Jun 29 07:24:16 PM PDT 24 109400700 ps
T247 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.976955068 Jun 29 07:23:13 PM PDT 24 Jun 29 07:23:28 PM PDT 24 55864600 ps
T306 /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.4020974883 Jun 29 07:23:41 PM PDT 24 Jun 29 07:23:58 PM PDT 24 412726200 ps
T1130 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.2117626095 Jun 29 07:24:14 PM PDT 24 Jun 29 07:24:33 PM PDT 24 371059700 ps
T336 /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.3269682046 Jun 29 07:24:20 PM PDT 24 Jun 29 07:24:35 PM PDT 24 129961200 ps
T1131 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.127190374 Jun 29 07:24:05 PM PDT 24 Jun 29 07:24:24 PM PDT 24 54617600 ps
T339 /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.521072118 Jun 29 07:24:20 PM PDT 24 Jun 29 07:24:36 PM PDT 24 108344900 ps
T1132 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.1453999775 Jun 29 07:23:34 PM PDT 24 Jun 29 07:23:48 PM PDT 24 11915500 ps
T259 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3473320658 Jun 29 07:23:13 PM PDT 24 Jun 29 07:31:00 PM PDT 24 343673800 ps
T278 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.355673401 Jun 29 07:24:07 PM PDT 24 Jun 29 07:40:12 PM PDT 24 703413500 ps
T1133 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.462361234 Jun 29 07:23:57 PM PDT 24 Jun 29 07:24:13 PM PDT 24 166434000 ps
T1134 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.322724939 Jun 29 07:23:33 PM PDT 24 Jun 29 07:23:50 PM PDT 24 13515200 ps
T248 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.3455223966 Jun 29 07:23:07 PM PDT 24 Jun 29 07:23:20 PM PDT 24 154557900 ps
T1135 /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.3734017124 Jun 29 07:24:23 PM PDT 24 Jun 29 07:24:38 PM PDT 24 17095000 ps
T340 /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.706791375 Jun 29 07:24:10 PM PDT 24 Jun 29 07:24:24 PM PDT 24 14570000 ps
T1136 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.212604790 Jun 29 07:23:05 PM PDT 24 Jun 29 07:23:22 PM PDT 24 41158500 ps
T1137 /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.13385222 Jun 29 07:24:29 PM PDT 24 Jun 29 07:24:43 PM PDT 24 37641300 ps
T1138 /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.1332553658 Jun 29 07:24:33 PM PDT 24 Jun 29 07:24:47 PM PDT 24 26384800 ps
T353 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2798812888 Jun 29 07:24:04 PM PDT 24 Jun 29 07:39:56 PM PDT 24 4411209500 ps
T249 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.888155134 Jun 29 07:23:23 PM PDT 24 Jun 29 07:23:38 PM PDT 24 88469800 ps
T1139 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1714652943 Jun 29 07:23:14 PM PDT 24 Jun 29 07:23:29 PM PDT 24 12986400 ps
T281 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.227296774 Jun 29 07:23:40 PM PDT 24 Jun 29 07:39:41 PM PDT 24 394858100 ps
T1140 /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.3808062114 Jun 29 07:24:23 PM PDT 24 Jun 29 07:24:37 PM PDT 24 15575200 ps
T275 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3697076087 Jun 29 07:24:24 PM PDT 24 Jun 29 07:30:59 PM PDT 24 1362680700 ps
T307 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.1984448713 Jun 29 07:23:40 PM PDT 24 Jun 29 07:23:54 PM PDT 24 133763500 ps
T1141 /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1704810028 Jun 29 07:24:14 PM PDT 24 Jun 29 07:24:33 PM PDT 24 1126074700 ps
T1142 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.3707565440 Jun 29 07:23:05 PM PDT 24 Jun 29 07:24:02 PM PDT 24 1347172900 ps
T1143 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2609473651 Jun 29 07:23:56 PM PDT 24 Jun 29 07:24:13 PM PDT 24 138888400 ps
T354 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.913046166 Jun 29 07:23:48 PM PDT 24 Jun 29 07:31:36 PM PDT 24 562563500 ps
T1144 /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.116489656 Jun 29 07:24:24 PM PDT 24 Jun 29 07:24:38 PM PDT 24 17274800 ps
T1145 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.3900873195 Jun 29 07:23:41 PM PDT 24 Jun 29 07:23:57 PM PDT 24 198971400 ps
T1146 /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.3360663166 Jun 29 07:24:22 PM PDT 24 Jun 29 07:24:37 PM PDT 24 18196100 ps
T1147 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2295282212 Jun 29 07:23:15 PM PDT 24 Jun 29 07:23:32 PM PDT 24 15261600 ps
T1148 /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.3146218216 Jun 29 07:24:30 PM PDT 24 Jun 29 07:24:44 PM PDT 24 17476400 ps
T279 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.1365004514 Jun 29 07:24:14 PM PDT 24 Jun 29 07:32:00 PM PDT 24 410104700 ps
T1149 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.2311707460 Jun 29 07:23:41 PM PDT 24 Jun 29 07:23:58 PM PDT 24 43433600 ps
T1150 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3800727250 Jun 29 07:24:15 PM PDT 24 Jun 29 07:24:30 PM PDT 24 24674200 ps
T274 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1281247471 Jun 29 07:24:12 PM PDT 24 Jun 29 07:24:29 PM PDT 24 37197100 ps
T1151 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.3842576049 Jun 29 07:24:15 PM PDT 24 Jun 29 07:24:29 PM PDT 24 123905100 ps
T1152 /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.3144203998 Jun 29 07:24:23 PM PDT 24 Jun 29 07:24:38 PM PDT 24 17001900 ps
T1153 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2030459827 Jun 29 07:23:50 PM PDT 24 Jun 29 07:24:07 PM PDT 24 14128100 ps
T1154 /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.3801532785 Jun 29 07:23:42 PM PDT 24 Jun 29 07:24:04 PM PDT 24 1894981300 ps
T1155 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.1091573311 Jun 29 07:23:57 PM PDT 24 Jun 29 07:24:14 PM PDT 24 57886600 ps
T266 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.328939449 Jun 29 07:23:14 PM PDT 24 Jun 29 07:23:35 PM PDT 24 59469100 ps
T1156 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.3108548802 Jun 29 07:23:51 PM PDT 24 Jun 29 07:24:07 PM PDT 24 18593200 ps
T1157 /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.1051702129 Jun 29 07:24:05 PM PDT 24 Jun 29 07:24:19 PM PDT 24 44825600 ps
T308 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1689547788 Jun 29 07:24:23 PM PDT 24 Jun 29 07:24:44 PM PDT 24 107790100 ps
T1158 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.2020559373 Jun 29 07:23:15 PM PDT 24 Jun 29 07:23:33 PM PDT 24 20756800 ps
T1159 /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.2789425979 Jun 29 07:24:31 PM PDT 24 Jun 29 07:24:46 PM PDT 24 14544800 ps
T1160 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2881501318 Jun 29 07:23:56 PM PDT 24 Jun 29 07:24:13 PM PDT 24 41859200 ps
T1161 /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.3728940404 Jun 29 07:24:18 PM PDT 24 Jun 29 07:24:32 PM PDT 24 104668700 ps
T267 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1334398758 Jun 29 07:24:13 PM PDT 24 Jun 29 07:24:30 PM PDT 24 33641100 ps
T276 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.4125951583 Jun 29 07:23:48 PM PDT 24 Jun 29 07:24:08 PM PDT 24 638764200 ps
T1162 /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.3980935213 Jun 29 07:24:31 PM PDT 24 Jun 29 07:24:47 PM PDT 24 30593000 ps
T277 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1077941271 Jun 29 07:23:23 PM PDT 24 Jun 29 07:23:44 PM PDT 24 258585400 ps
T309 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.4218104052 Jun 29 07:23:23 PM PDT 24 Jun 29 07:24:04 PM PDT 24 806709300 ps
T310 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.1630802423 Jun 29 07:23:59 PM PDT 24 Jun 29 07:24:17 PM PDT 24 79847100 ps
T1163 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.3990351277 Jun 29 07:23:24 PM PDT 24 Jun 29 07:23:39 PM PDT 24 19334600 ps
T250 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.2251177215 Jun 29 07:23:23 PM PDT 24 Jun 29 07:23:38 PM PDT 24 20796100 ps
T1164 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.1773669733 Jun 29 07:23:50 PM PDT 24 Jun 29 07:24:05 PM PDT 24 20322800 ps
T271 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.3425443415 Jun 29 07:23:32 PM PDT 24 Jun 29 07:23:51 PM PDT 24 144030500 ps
T311 /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3505120176 Jun 29 07:23:10 PM PDT 24 Jun 29 07:23:29 PM PDT 24 205822200 ps
T1165 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2603085854 Jun 29 07:23:48 PM PDT 24 Jun 29 07:24:04 PM PDT 24 14413300 ps
T356 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2472687062 Jun 29 07:23:56 PM PDT 24 Jun 29 07:39:49 PM PDT 24 891198500 ps
T1166 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2750933944 Jun 29 07:23:07 PM PDT 24 Jun 29 07:23:53 PM PDT 24 90855200 ps
T1167 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.993488489 Jun 29 07:24:12 PM PDT 24 Jun 29 07:24:31 PM PDT 24 179568700 ps
T1168 /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.205439560 Jun 29 07:23:48 PM PDT 24 Jun 29 07:24:03 PM PDT 24 16101700 ps
T1169 /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2495052596 Jun 29 07:24:28 PM PDT 24 Jun 29 07:24:42 PM PDT 24 15843500 ps
T1170 /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.1755906773 Jun 29 07:24:22 PM PDT 24 Jun 29 07:24:38 PM PDT 24 59488900 ps
T1171 /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.1776752769 Jun 29 07:23:39 PM PDT 24 Jun 29 07:23:53 PM PDT 24 17295200 ps
T312 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1322804109 Jun 29 07:24:22 PM PDT 24 Jun 29 07:24:42 PM PDT 24 185687200 ps
T1172 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3395790048 Jun 29 07:24:22 PM PDT 24 Jun 29 07:24:40 PM PDT 24 54335700 ps
T313 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1661704794 Jun 29 07:24:20 PM PDT 24 Jun 29 07:40:39 PM PDT 24 3157469300 ps
T314 /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.680673574 Jun 29 07:24:04 PM PDT 24 Jun 29 07:24:35 PM PDT 24 199621100 ps
T315 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.3786885151 Jun 29 07:23:16 PM PDT 24 Jun 29 07:24:29 PM PDT 24 3477312900 ps
T1173 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2184032301 Jun 29 07:23:26 PM PDT 24 Jun 29 07:24:12 PM PDT 24 60885600 ps
T1174 /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.1183079980 Jun 29 07:23:56 PM PDT 24 Jun 29 07:24:13 PM PDT 24 89648500 ps
T1175 /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.122662555 Jun 29 07:24:33 PM PDT 24 Jun 29 07:24:47 PM PDT 24 26009800 ps
T1176 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.2719143064 Jun 29 07:24:06 PM PDT 24 Jun 29 07:24:23 PM PDT 24 25074100 ps
T1177 /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.2653810348 Jun 29 07:24:32 PM PDT 24 Jun 29 07:24:47 PM PDT 24 54023300 ps
T1178 /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.3531444610 Jun 29 07:23:15 PM PDT 24 Jun 29 07:23:29 PM PDT 24 71529100 ps
T1179 /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.600360904 Jun 29 07:24:20 PM PDT 24 Jun 29 07:24:35 PM PDT 24 16001000 ps
T1180 /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.2714804526 Jun 29 07:24:06 PM PDT 24 Jun 29 07:24:24 PM PDT 24 130945800 ps
T283 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2776769037 Jun 29 07:23:43 PM PDT 24 Jun 29 07:24:00 PM PDT 24 37434300 ps
T1181 /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.1303210009 Jun 29 07:23:39 PM PDT 24 Jun 29 07:23:53 PM PDT 24 51032400 ps
T1182 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.2475359457 Jun 29 07:24:20 PM PDT 24 Jun 29 07:24:37 PM PDT 24 14334500 ps
T1183 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.729088383 Jun 29 07:24:14 PM PDT 24 Jun 29 07:24:31 PM PDT 24 21281100 ps
T1184 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.1638498777 Jun 29 07:24:21 PM PDT 24 Jun 29 07:24:38 PM PDT 24 41349600 ps
T272 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.397496694 Jun 29 07:23:49 PM PDT 24 Jun 29 07:24:05 PM PDT 24 85293000 ps
T316 /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.2989641391 Jun 29 07:23:50 PM PDT 24 Jun 29 07:24:27 PM PDT 24 190294900 ps
T1185 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.3258169808 Jun 29 07:23:15 PM PDT 24 Jun 29 07:23:31 PM PDT 24 38078600 ps
T1186 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3982144208 Jun 29 07:23:57 PM PDT 24 Jun 29 07:24:14 PM PDT 24 12198900 ps
T1187 /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.3655826635 Jun 29 07:24:24 PM PDT 24 Jun 29 07:24:40 PM PDT 24 38320200 ps
T1188 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.3362270033 Jun 29 07:23:48 PM PDT 24 Jun 29 07:30:20 PM PDT 24 1542858700 ps
T1189 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.600090195 Jun 29 07:23:51 PM PDT 24 Jun 29 07:24:07 PM PDT 24 23664700 ps
T1190 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.464294479 Jun 29 07:23:33 PM PDT 24 Jun 29 07:24:54 PM PDT 24 9742840400 ps
T1191 /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.3242518035 Jun 29 07:24:29 PM PDT 24 Jun 29 07:24:44 PM PDT 24 16945800 ps
T1192 /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.19861128 Jun 29 07:23:33 PM PDT 24 Jun 29 07:23:51 PM PDT 24 80670300 ps
T282 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.1835486910 Jun 29 07:24:15 PM PDT 24 Jun 29 07:32:00 PM PDT 24 445328100 ps
T1193 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2624742170 Jun 29 07:24:10 PM PDT 24 Jun 29 07:24:28 PM PDT 24 110256300 ps
T1194 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2949556465 Jun 29 07:24:14 PM PDT 24 Jun 29 07:24:33 PM PDT 24 198620000 ps
T1195 /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.1613044673 Jun 29 07:24:31 PM PDT 24 Jun 29 07:24:47 PM PDT 24 15116000 ps
T1196 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3093486845 Jun 29 07:23:32 PM PDT 24 Jun 29 07:24:59 PM PDT 24 4653584000 ps
T317 /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1631999145 Jun 29 07:24:03 PM PDT 24 Jun 29 07:24:23 PM PDT 24 386586000 ps
T1197 /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.1938635009 Jun 29 07:23:32 PM PDT 24 Jun 29 07:23:54 PM PDT 24 333912600 ps
T1198 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.1502430412 Jun 29 07:24:22 PM PDT 24 Jun 29 07:24:41 PM PDT 24 97213700 ps
T1199 /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.1993530722 Jun 29 07:23:33 PM PDT 24 Jun 29 07:23:47 PM PDT 24 18142200 ps
T1200 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.2958308562 Jun 29 07:23:42 PM PDT 24 Jun 29 07:31:29 PM PDT 24 439314600 ps
T1201 /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2764304784 Jun 29 07:24:30 PM PDT 24 Jun 29 07:24:45 PM PDT 24 70547200 ps
T1202 /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.627974791 Jun 29 07:24:04 PM PDT 24 Jun 29 07:24:19 PM PDT 24 22251500 ps
T1203 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1967023833 Jun 29 07:24:22 PM PDT 24 Jun 29 07:24:40 PM PDT 24 37257900 ps
T1204 /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.1462085824 Jun 29 07:23:48 PM PDT 24 Jun 29 07:24:04 PM PDT 24 20021500 ps
T1205 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.1818427794 Jun 29 07:23:23 PM PDT 24 Jun 29 07:23:55 PM PDT 24 38232900 ps
T1206 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.3889533279 Jun 29 07:23:48 PM PDT 24 Jun 29 07:24:06 PM PDT 24 24984800 ps
T1207 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.47980151 Jun 29 07:24:30 PM PDT 24 Jun 29 07:24:45 PM PDT 24 46353200 ps
T318 /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.2485317595 Jun 29 07:23:56 PM PDT 24 Jun 29 07:24:32 PM PDT 24 1036457800 ps
T1208 /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2011573095 Jun 29 07:23:13 PM PDT 24 Jun 29 07:23:37 PM PDT 24 1995503700 ps
T359 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.1602130334 Jun 29 07:23:35 PM PDT 24 Jun 29 07:31:24 PM PDT 24 328663100 ps
T1209 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.14289602 Jun 29 07:24:05 PM PDT 24 Jun 29 07:24:20 PM PDT 24 35588700 ps
T1210 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1260643175 Jun 29 07:23:49 PM PDT 24 Jun 29 07:24:07 PM PDT 24 13412000 ps
T1211 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.90861021 Jun 29 07:23:24 PM PDT 24 Jun 29 07:24:19 PM PDT 24 6842208600 ps
T1212 /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.4004782557 Jun 29 07:24:30 PM PDT 24 Jun 29 07:24:44 PM PDT 24 17018400 ps
T1213 /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.2411105265 Jun 29 07:24:12 PM PDT 24 Jun 29 07:24:26 PM PDT 24 29618000 ps
T1214 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.231969610 Jun 29 07:23:23 PM PDT 24 Jun 29 07:23:37 PM PDT 24 76381200 ps
T1215 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.391754562 Jun 29 07:23:58 PM PDT 24 Jun 29 07:24:16 PM PDT 24 328108600 ps
T1216 /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1684063579 Jun 29 07:24:33 PM PDT 24 Jun 29 07:24:47 PM PDT 24 50082100 ps
T1217 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.4042667924 Jun 29 07:24:22 PM PDT 24 Jun 29 07:24:36 PM PDT 24 13334500 ps
T280 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.1679348471 Jun 29 07:24:03 PM PDT 24 Jun 29 07:24:21 PM PDT 24 35919800 ps
T1218 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1676359925 Jun 29 07:23:08 PM PDT 24 Jun 29 07:23:22 PM PDT 24 132339900 ps
T1219 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2320688512 Jun 29 07:23:13 PM PDT 24 Jun 29 07:23:29 PM PDT 24 33666800 ps
T355 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.3407479970 Jun 29 07:23:10 PM PDT 24 Jun 29 07:30:52 PM PDT 24 836431500 ps
T1220 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1246369329 Jun 29 07:23:40 PM PDT 24 Jun 29 07:24:01 PM PDT 24 48461900 ps
T1221 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.3141206432 Jun 29 07:24:23 PM PDT 24 Jun 29 07:24:41 PM PDT 24 107651800 ps
T1222 /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3640593823 Jun 29 07:24:24 PM PDT 24 Jun 29 07:24:38 PM PDT 24 27042400 ps
T1223 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.4054044907 Jun 29 07:23:22 PM PDT 24 Jun 29 07:23:39 PM PDT 24 23760900 ps
T1224 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2307552398 Jun 29 07:23:14 PM PDT 24 Jun 29 07:23:34 PM PDT 24 49807800 ps
T284 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2382435300 Jun 29 07:23:57 PM PDT 24 Jun 29 07:40:09 PM PDT 24 1432061600 ps
T319 /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.1663110095 Jun 29 07:23:51 PM PDT 24 Jun 29 07:24:10 PM PDT 24 120070400 ps
T1225 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.417480641 Jun 29 07:23:50 PM PDT 24 Jun 29 07:24:06 PM PDT 24 95399800 ps
T1226 /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.2520302396 Jun 29 07:24:21 PM PDT 24 Jun 29 07:24:42 PM PDT 24 204512800 ps
T1227 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.2668268540 Jun 29 07:23:48 PM PDT 24 Jun 29 07:24:07 PM PDT 24 80699500 ps
T1228 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.634900884 Jun 29 07:23:16 PM PDT 24 Jun 29 07:23:35 PM PDT 24 339474100 ps
T1229 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.410106704 Jun 29 07:24:22 PM PDT 24 Jun 29 07:24:40 PM PDT 24 14024300 ps
T1230 /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.3863904432 Jun 29 07:24:22 PM PDT 24 Jun 29 07:24:46 PM PDT 24 825054200 ps
T1231 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2800570624 Jun 29 07:23:30 PM PDT 24 Jun 29 07:24:06 PM PDT 24 233296900 ps
T1232 /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3711526924 Jun 29 07:24:30 PM PDT 24 Jun 29 07:24:45 PM PDT 24 79486000 ps
T1233 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.3988761716 Jun 29 07:24:22 PM PDT 24 Jun 29 07:24:40 PM PDT 24 39538400 ps
T1234 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.3451805542 Jun 29 07:23:41 PM PDT 24 Jun 29 07:23:57 PM PDT 24 35530100 ps
T1235 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2572299164 Jun 29 07:23:23 PM PDT 24 Jun 29 07:23:39 PM PDT 24 101316700 ps
T1236 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.804142677 Jun 29 07:23:41 PM PDT 24 Jun 29 07:24:01 PM PDT 24 123589100 ps
T1237 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.2775261571 Jun 29 07:23:33 PM PDT 24 Jun 29 07:23:48 PM PDT 24 246718800 ps
T1238 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.792356790 Jun 29 07:24:04 PM PDT 24 Jun 29 07:24:21 PM PDT 24 56834200 ps
T1239 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1629502501 Jun 29 07:23:51 PM PDT 24 Jun 29 07:24:08 PM PDT 24 32299200 ps
T1240 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.3621172066 Jun 29 07:24:07 PM PDT 24 Jun 29 07:24:25 PM PDT 24 137084000 ps
T1241 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.2227829829 Jun 29 07:24:13 PM PDT 24 Jun 29 07:32:01 PM PDT 24 707304100 ps
T358 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.2652565635 Jun 29 07:23:23 PM PDT 24 Jun 29 07:39:16 PM PDT 24 358350700 ps
T1242 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.2288519186 Jun 29 07:24:21 PM PDT 24 Jun 29 07:24:39 PM PDT 24 42382400 ps
T1243 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.2484858299 Jun 29 07:24:10 PM PDT 24 Jun 29 07:24:26 PM PDT 24 38437300 ps
T1244 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3452690938 Jun 29 07:24:17 PM PDT 24 Jun 29 07:24:32 PM PDT 24 408616200 ps
T1245 /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.3978369959 Jun 29 07:24:13 PM PDT 24 Jun 29 07:24:49 PM PDT 24 66650700 ps
T1246 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2773143688 Jun 29 07:24:14 PM PDT 24 Jun 29 07:24:33 PM PDT 24 24785700 ps
T1247 /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.4197053609 Jun 29 07:24:29 PM PDT 24 Jun 29 07:24:44 PM PDT 24 50776700 ps
T1248 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.2592372683 Jun 29 07:23:32 PM PDT 24 Jun 29 07:23:47 PM PDT 24 26749600 ps
T1249 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.963466575 Jun 29 07:23:33 PM PDT 24 Jun 29 07:24:20 PM PDT 24 165229700 ps
T1250 /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.2591674217 Jun 29 07:24:33 PM PDT 24 Jun 29 07:24:48 PM PDT 24 73080700 ps
T1251 /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.2955145191 Jun 29 07:24:31 PM PDT 24 Jun 29 07:24:47 PM PDT 24 16250000 ps
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