Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	351126	1		T2	2		T3	1		T4	2
all_values[1]	351126	1		T2	2		T3	1		T4	2
all_values[2]	351126	1		T2	2		T3	1		T4	2
all_values[3]	351126	1		T2	2		T3	1		T4	2
all_values[4]	351126	1		T2	2		T3	1		T4	2
all_values[5]	351126	1		T2	2		T3	1		T4	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	708577	1		T2	12		T3	6		T4	12
auto[1]	1398179	1		T5	6412		T25	5836		T28	2712

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1029929	1		T2	7		T3	4		T4	6
auto[1]	1076827	1		T2	5		T3	2		T4	6

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	350976	1		T2	2		T3	1		T4	2
all_values[0]	auto[1]	auto[1]	150	1		T264	7		T265	7		T339	2
all_values[1]	auto[0]	auto[1]	350983	1		T2	2		T3	1		T4	2
all_values[1]	auto[1]	auto[1]	143	1		T263	4		T264	5		T265	5
all_values[2]	auto[0]	auto[0]	1597	1		T2	2		T3	1		T4	2
all_values[2]	auto[0]	auto[1]	53	1		T264	1		T265	1		T339	1
all_values[2]	auto[1]	auto[0]	349423	1		T5	1603		T25	1459		T28	678
all_values[2]	auto[1]	auto[1]	53	1		T263	1		T264	1		T265	1
all_values[3]	auto[0]	auto[0]	1616	1		T2	2		T3	1		T4	2
all_values[3]	auto[0]	auto[1]	59	1		T263	2		T264	2		T265	2
all_values[3]	auto[1]	auto[0]	78331	1		T5	1603		T25	1459		T28	339
all_values[3]	auto[1]	auto[1]	271120	1		T28	339		T32	3116		T33	2120
all_values[4]	auto[0]	auto[0]	1107	1		T2	1		T3	1		T4	1
all_values[4]	auto[0]	auto[1]	532	1		T2	1		T4	1		T10	1
all_values[4]	auto[1]	auto[0]	246940	1		T5	1		T25	1		T28	339
all_values[4]	auto[1]	auto[1]	102547	1		T5	1602		T25	1458		T28	339
all_values[5]	auto[0]	auto[0]	1503	1		T2	2		T3	1		T4	1
all_values[5]	auto[0]	auto[1]	151	1		T4	1		T34	1		T35	1
all_values[5]	auto[1]	auto[0]	349412	1		T5	1603		T25	1459		T28	678
all_values[5]	auto[1]	auto[1]	60	1		T263	1		T265	1		T339	1