Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	1	15	93.75

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	1	15	93.75	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	239059	1		T2	1767		T4	680		T10	2
auto[FlashEraseBank]	264883	1		T2	1757		T4	688		T5	875

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	258009	1		T2	1310		T4	1368		T12	1
auto[FlashOpProgram]	226348	1		T2	2214		T5	1602		T17	2
auto[FlashOpErase]	15585	1		T10	2		T18	55		T22	15
auto[FlashOpInvalid]	4000	1		T43	200		T130	200		T277	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	258009	1		T2	1310		T4	1368		T12	1
op[FlashOpProgram]	226348	1		T2	2214		T5	1602		T17	2
op[FlashOpErase]	15585	1		T10	2		T18	55		T22	15
read_erase_read	531	1		T18	3		T22	12		T27	2
read_prog_read	918	1		T2	9		T18	1		T55	5

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	365342	1		T2	2990		T4	1166		T5	1394
auto[FlashPartInfo]	134935	1		T2	520		T4	198		T10	1
auto[FlashPartInfo1]	965	1		T2	1		T4	2		T6	2
auto[FlashPartInfo2]	2700	1		T2	13		T4	2		T10	1

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for op_part_cross

Uncovered bins

part_cp	op_cp	COUNT	AT LEAST	NUMBER
[auto[FlashPartInfo1]]	[auto[FlashOpInvalid]]	0	1	1

Covered bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	187756	1		T2	1009		T4	1166		T12	1
auto[FlashPartData]	auto[FlashOpProgram]	170110	1		T2	1981		T5	1394		T17	2
auto[FlashPartData]	auto[FlashOpErase]	3558	1		T18	40		T22	4		T27	37
auto[FlashPartData]	auto[FlashOpInvalid]	3918	1		T43	194		T130	192		T277	200
auto[FlashPartInfo]	auto[FlashOpRead]	67660	1		T2	290		T4	198		T6	280
auto[FlashPartInfo]	auto[FlashOpProgram]	55214	1		T2	230		T5	207		T18	544
auto[FlashPartInfo]	auto[FlashOpErase]	11991	1		T10	1		T18	15		T22	11
auto[FlashPartInfo]	auto[FlashOpInvalid]	70	1		T43	6		T130	4		T122	4
auto[FlashPartInfo1]	auto[FlashOpRead]	796	1		T2	1		T4	2		T6	2
auto[FlashPartInfo1]	auto[FlashOpProgram]	163	1		T141	32		T142	32		T120	1
auto[FlashPartInfo1]	auto[FlashOpErase]	6	1		T71	1		T357	1		T116	1
auto[FlashPartInfo2]	auto[FlashOpRead]	1797	1		T2	10		T4	2		T6	3
auto[FlashPartInfo2]	auto[FlashOpProgram]	861	1		T2	3		T5	1		T55	8
auto[FlashPartInfo2]	auto[FlashOpErase]	30	1		T10	1		T40	1		T130	2
auto[FlashPartInfo2]	auto[FlashOpInvalid]	12	1		T130	4		T358	2		T359	2