Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30949	1		T18	16		T27	20		T48	556
auto[1]	42	1		T135	2		T37	1		T136	14
auto[2]	100	1		T22	14		T278	7		T138	2
auto[3]	231	1		T21	1		T23	1		T135	9

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7848	1		T18	4		T22	4		T27	5
evic_idx[1]	7823	1		T18	4		T22	4		T27	5
evic_idx[2]	7833	1		T18	4		T21	1		T22	4
evic_idx[3]	7818	1		T18	4		T22	2		T27	5

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	30360	1		T22	14		T48	556		T43	400
evic_op[2]	338	1		T21	1		T27	4		T23	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7516	1		T48	139		T43	100		T130	100
evic_idx[0]	evic_op[1]	auto[1]	11	1		T135	1		T136	5		T138	1
evic_idx[0]	evic_op[1]	auto[2]	20	1		T22	4		T212	2		T401	5
evic_idx[0]	evic_op[1]	auto[3]	53	1		T135	3		T283	2		T138	1
evic_idx[0]	evic_op[2]	auto[0]	73	1		T27	1		T224	4		T225	4
evic_idx[0]	evic_op[2]	auto[1]	2	1		T37	1		T402	1		-	-
evic_idx[0]	evic_op[2]	auto[2]	4	1		T278	2		T403	2		-	-
evic_idx[0]	evic_op[2]	auto[3]	13	1		T23	1		T213	1		T206	1
evic_idx[1]	evic_op[1]	auto[0]	7522	1		T48	139		T43	100		T130	100
evic_idx[1]	evic_op[1]	auto[1]	7	1		T136	3		T138	1		T212	1
evic_idx[1]	evic_op[1]	auto[2]	13	1		T22	4		T212	1		T401	3
evic_idx[1]	evic_op[1]	auto[3]	44	1		T135	2		T283	2		T138	1
evic_idx[1]	evic_op[2]	auto[0]	67	1		T27	1		T224	4		T225	4
evic_idx[1]	evic_op[2]	auto[1]	1	1		T404	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[2]	5	1		T278	2		T298	1		T405	1
evic_idx[1]	evic_op[2]	auto[3]	8	1		T207	1		T406	1		T407	1
evic_idx[2]	evic_op[1]	auto[0]	7519	1		T48	139		T43	100		T130	100
evic_idx[2]	evic_op[1]	auto[1]	10	1		T135	1		T136	4		T138	1
evic_idx[2]	evic_op[1]	auto[2]	18	1		T22	4		T138	1		T212	1
evic_idx[2]	evic_op[1]	auto[3]	48	1		T135	2		T136	1		T283	4
evic_idx[2]	evic_op[2]	auto[0]	66	1		T27	1		T224	4		T225	4
evic_idx[2]	evic_op[2]	auto[1]	1	1		T408	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[2]	3	1		T206	1		T409	1		T405	1
evic_idx[2]	evic_op[2]	auto[3]	12	1		T21	1		T280	1		T295	1
evic_idx[3]	evic_op[1]	auto[0]	7518	1		T48	139		T43	100		T130	100
evic_idx[3]	evic_op[1]	auto[1]	8	1		T136	2		T138	1		T401	1
evic_idx[3]	evic_op[1]	auto[2]	10	1		T22	2		T138	1		T212	1
evic_idx[3]	evic_op[1]	auto[3]	43	1		T135	2		T136	1		T283	2
evic_idx[3]	evic_op[2]	auto[0]	68	1		T27	1		T224	4		T225	4
evic_idx[3]	evic_op[2]	auto[1]	2	1		T410	1		T411	1		-	-
evic_idx[3]	evic_op[2]	auto[2]	3	1		T278	3		-	-		-	-
evic_idx[3]	evic_op[2]	auto[3]	10	1		T278	1		T250	1		T412	1