Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	26890	1		T347	15699		T348	1237		T349	2767
rd_lvl[2]	70279	1		T350	12524		T347	11469		T351	11486
rd_lvl[3]	14626	1		T352	1481		T350	390		T353	4371
rd_lvl[4]	36310	1		T33	1372		T352	5719		T353	3979
rd_lvl[5]	20575	1		T33	453		T352	878		T281	1646
rd_lvl[6]	15919	1		T32	2303		T33	43		T334	768
rd_lvl[7]	10204	1		T32	813		T33	101		T334	167
rd_lvl[8]	10960	1		T33	90		T285	2889		T334	1
rd_lvl[9]	8634	1		T354	645		T285	339		T334	12
rd_lvl[10]	7498	1		T354	1070		T334	12		T289	1
rd_lvl[11]	3854	1		T33	1		T290	194		T293	276
rd_lvl[12]	6456	1		T33	49		T296	1352		T290	1393
rd_lvl[13]	1594	1		T296	370		T289	42		T355	338
rd_lvl[14]	5407	1		T28	249		T30	61		T356	1375
rd_lvl[15]	3957	1		T28	89		T30	17		T356	303