Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	351126	1		T2	2		T3	1		T4	2
all_pins[1]	351126	1		T2	2		T3	1		T4	2
all_pins[2]	351126	1		T2	2		T3	1		T4	2
all_pins[3]	351126	1		T2	2		T3	1		T4	2
all_pins[4]	351126	1		T2	2		T3	1		T4	2
all_pins[5]	351126	1		T2	2		T3	1		T4	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1746066	1		T2	12		T3	6		T4	12
values[0x1]	360690	1		T5	1602		T25	1458		T28	680
transitions[0x0=>0x1]	324943	1		T5	1602		T25	1458		T28	678
transitions[0x1=>0x0]	324936	1		T5	1602		T25	1458		T28	678

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	350976	1		T2	2		T3	1		T4	2
all_pins[0]	values[0x1]	150	1		T264	7		T265	7		T339	2
all_pins[0]	transitions[0x0=>0x1]	71	1		T264	3		T265	3		T339	2
all_pins[0]	transitions[0x1=>0x0]	64	1		T263	4		T264	1		T265	1
all_pins[1]	values[0x0]	350983	1		T2	2		T3	1		T4	2
all_pins[1]	values[0x1]	143	1		T263	4		T264	5		T265	5
all_pins[1]	transitions[0x0=>0x1]	116	1		T263	3		T264	4		T265	4
all_pins[1]	transitions[0x1=>0x0]	2970	1		T28	1		T30	1		T31	1081
all_pins[2]	values[0x0]	348129	1		T2	2		T3	1		T4	2
all_pins[2]	values[0x1]	2997	1		T28	1		T30	1		T31	1081
all_pins[2]	transitions[0x0=>0x1]	37	1		T265	1		T339	1		T341	1
all_pins[2]	transitions[0x1=>0x0]	243286	1		T28	338		T32	3116		T33	2109
all_pins[3]	values[0x0]	104880	1		T2	2		T3	1		T4	2
all_pins[3]	values[0x1]	246246	1		T28	339		T32	3116		T33	2109
all_pins[3]	transitions[0x0=>0x1]	213619	1		T28	338		T32	3116		T33	1475
all_pins[3]	transitions[0x1=>0x0]	78467	1		T5	1602		T25	1458		T28	339
all_pins[4]	values[0x0]	240032	1		T2	2		T3	1		T4	2
all_pins[4]	values[0x1]	111094	1		T5	1602		T25	1458		T28	340
all_pins[4]	transitions[0x0=>0x1]	111080	1		T5	1602		T25	1458		T28	340
all_pins[4]	transitions[0x1=>0x0]	46	1		T263	1		T345	3		T346	3
all_pins[5]	values[0x0]	351066	1		T2	2		T3	1		T4	2
all_pins[5]	values[0x1]	60	1		T263	1		T265	1		T339	1
all_pins[5]	transitions[0x0=>0x1]	20	1		T345	2		T346	1		T360	1
all_pins[5]	transitions[0x1=>0x0]	103	1		T264	6		T265	6		T339	1