Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	275	1		T263	4		T264	7		T265	7
all_values[1]	275	1		T263	4		T264	7		T265	7
all_values[2]	275	1		T263	4		T264	7		T265	7
all_values[3]	275	1		T263	4		T264	7		T265	7
all_values[4]	275	1		T263	4		T264	7		T265	7
all_values[5]	275	1		T263	4		T264	7		T265	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	938	1		T263	8		T264	22		T265	25
auto[1]	712	1		T263	16		T264	20		T265	17

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	543	1		T263	10		T264	17		T265	11
auto[1]	1107	1		T263	14		T264	25		T265	31

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1003	1		T263	18		T264	30		T265	25
auto[1]	647	1		T263	6		T264	12		T265	17

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	92	1		T263	3		T265	2		T339	1
all_values[0]	auto[0]	auto[1]	auto[1]	86	1		T264	5		T265	3		T339	2
all_values[0]	auto[1]	auto[0]	auto[1]	56	1		T263	1		T264	1		T265	1
all_values[0]	auto[1]	auto[1]	auto[1]	41	1		T264	1		T265	1		T340	1
all_values[1]	auto[0]	auto[0]	auto[1]	93	1		T264	2		T265	2		T339	1
all_values[1]	auto[0]	auto[1]	auto[1]	72	1		T263	4		T264	3		T265	2
all_values[1]	auto[1]	auto[0]	auto[1]	61	1		T264	1		T265	1		T339	2
all_values[1]	auto[1]	auto[1]	auto[1]	49	1		T264	1		T265	2		T339	1
all_values[2]	auto[0]	auto[0]	auto[0]	100	1		T263	2		T264	4		T265	2
all_values[2]	auto[0]	auto[1]	auto[0]	69	1		T263	1		T264	1		T265	3
all_values[2]	auto[1]	auto[0]	auto[1]	57	1		T264	2		T265	1		T339	1
all_values[2]	auto[1]	auto[1]	auto[1]	49	1		T263	1		T265	1		T339	1
all_values[3]	auto[0]	auto[0]	auto[0]	105	1		T263	1		T264	1		T265	4
all_values[3]	auto[0]	auto[1]	auto[0]	59	1		T264	2		T339	1		T341	2
all_values[3]	auto[1]	auto[0]	auto[1]	70	1		T263	1		T264	2		T265	3
all_values[3]	auto[1]	auto[1]	auto[1]	41	1		T263	2		T264	2		T339	1
all_values[4]	auto[0]	auto[0]	auto[0]	48	1		T264	3		T339	2		T342	1
all_values[4]	auto[0]	auto[0]	auto[1]	30	1		T264	3		T265	1		T341	1
all_values[4]	auto[0]	auto[1]	auto[0]	49	1		T263	4		T340	2		T343	2
all_values[4]	auto[0]	auto[1]	auto[1]	31	1		T265	3		T341	2		T344	3
all_values[4]	auto[1]	auto[0]	auto[1]	71	1		T264	1		T265	2		T339	1
all_values[4]	auto[1]	auto[1]	auto[1]	46	1		T265	1		T339	1		T341	2
all_values[5]	auto[0]	auto[0]	auto[0]	66	1		T264	1		T265	1		T339	3
all_values[5]	auto[0]	auto[0]	auto[1]	32	1		T265	1		T341	1		T343	1
all_values[5]	auto[0]	auto[1]	auto[0]	47	1		T263	2		T264	5		T265	1
all_values[5]	auto[0]	auto[1]	auto[1]	24	1		T263	1		T345	1		T346	1
all_values[5]	auto[1]	auto[0]	auto[1]	57	1		T264	1		T265	4		T340	1
all_values[5]	auto[1]	auto[1]	auto[1]	49	1		T263	1		T339	1		T343	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal