| T1068 |
/workspace/coverage/default/23.flash_ctrl_otp_reset.1287190878 |
|
|
Jun 30 05:40:08 PM PDT 24 |
Jun 30 05:42:23 PM PDT 24 |
68672200 ps |
| T1069 |
/workspace/coverage/default/2.flash_ctrl_read_word_sweep_serr.974395519 |
|
|
Jun 30 05:34:48 PM PDT 24 |
Jun 30 05:35:18 PM PDT 24 |
83771500 ps |
| T1070 |
/workspace/coverage/default/15.flash_ctrl_rand_ops.1686046284 |
|
|
Jun 30 05:38:41 PM PDT 24 |
Jun 30 05:57:22 PM PDT 24 |
264677500 ps |
| T1071 |
/workspace/coverage/default/8.flash_ctrl_otp_reset.291963286 |
|
|
Jun 30 05:37:04 PM PDT 24 |
Jun 30 05:39:19 PM PDT 24 |
63348800 ps |
| T1072 |
/workspace/coverage/default/38.flash_ctrl_rw_evict_all_en.2600413048 |
|
|
Jun 30 05:41:40 PM PDT 24 |
Jun 30 05:42:12 PM PDT 24 |
76352500 ps |
| T1073 |
/workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.1983858698 |
|
|
Jun 30 05:41:10 PM PDT 24 |
Jun 30 05:46:18 PM PDT 24 |
24954485500 ps |
| T1074 |
/workspace/coverage/default/49.flash_ctrl_sec_info_access.4089131533 |
|
|
Jun 30 05:42:15 PM PDT 24 |
Jun 30 05:43:40 PM PDT 24 |
1978070800 ps |
| T1075 |
/workspace/coverage/default/19.flash_ctrl_sec_info_access.2788986496 |
|
|
Jun 30 05:39:47 PM PDT 24 |
Jun 30 05:40:44 PM PDT 24 |
473440000 ps |
| T1076 |
/workspace/coverage/default/25.flash_ctrl_rw_evict_all_en.130024240 |
|
|
Jun 30 05:40:28 PM PDT 24 |
Jun 30 05:41:01 PM PDT 24 |
68949300 ps |
| T1077 |
/workspace/coverage/default/38.flash_ctrl_smoke.1329057035 |
|
|
Jun 30 05:41:40 PM PDT 24 |
Jun 30 05:44:56 PM PDT 24 |
164850000 ps |
| T1078 |
/workspace/coverage/default/26.flash_ctrl_connect.3119425788 |
|
|
Jun 30 05:40:35 PM PDT 24 |
Jun 30 05:40:52 PM PDT 24 |
33228700 ps |
| T1079 |
/workspace/coverage/default/22.flash_ctrl_alert_test.408559180 |
|
|
Jun 30 05:40:07 PM PDT 24 |
Jun 30 05:40:21 PM PDT 24 |
63626000 ps |
| T1080 |
/workspace/coverage/default/8.flash_ctrl_intr_wr_slow_flash.2072691867 |
|
|
Jun 30 05:37:11 PM PDT 24 |
Jun 30 05:40:36 PM PDT 24 |
23754162300 ps |
| T1081 |
/workspace/coverage/default/21.flash_ctrl_rw_evict_all_en.1646324341 |
|
|
Jun 30 05:39:52 PM PDT 24 |
Jun 30 05:40:24 PM PDT 24 |
32661700 ps |
| T1082 |
/workspace/coverage/default/12.flash_ctrl_sec_info_access.1980550884 |
|
|
Jun 30 05:38:21 PM PDT 24 |
Jun 30 05:39:34 PM PDT 24 |
1899521300 ps |
| T1083 |
/workspace/coverage/default/27.flash_ctrl_smoke.3322335372 |
|
|
Jun 30 05:40:35 PM PDT 24 |
Jun 30 05:42:38 PM PDT 24 |
24077200 ps |
| T1084 |
/workspace/coverage/default/2.flash_ctrl_connect.2619380686 |
|
|
Jun 30 05:34:59 PM PDT 24 |
Jun 30 05:35:16 PM PDT 24 |
16877700 ps |
| T1085 |
/workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.2379592314 |
|
|
Jun 30 05:36:39 PM PDT 24 |
Jun 30 05:40:14 PM PDT 24 |
108773408700 ps |
| T1086 |
/workspace/coverage/default/5.flash_ctrl_connect.2989369858 |
|
|
Jun 30 05:36:20 PM PDT 24 |
Jun 30 05:36:36 PM PDT 24 |
27903000 ps |
| T1087 |
/workspace/coverage/default/37.flash_ctrl_alert_test.3953295752 |
|
|
Jun 30 05:41:39 PM PDT 24 |
Jun 30 05:41:54 PM PDT 24 |
65992900 ps |
| T1088 |
/workspace/coverage/default/30.flash_ctrl_hw_sec_otp.996211590 |
|
|
Jun 30 05:40:52 PM PDT 24 |
Jun 30 05:45:21 PM PDT 24 |
8735716400 ps |
| T1089 |
/workspace/coverage/default/6.flash_ctrl_hw_sec_otp.1983144873 |
|
|
Jun 30 05:36:30 PM PDT 24 |
Jun 30 05:40:16 PM PDT 24 |
9262459400 ps |
| T1090 |
/workspace/coverage/default/36.flash_ctrl_rw_evict_all_en.4212659258 |
|
|
Jun 30 05:41:23 PM PDT 24 |
Jun 30 05:41:55 PM PDT 24 |
80216600 ps |
| T1091 |
/workspace/coverage/default/4.flash_ctrl_mp_regions.434180178 |
|
|
Jun 30 05:35:48 PM PDT 24 |
Jun 30 05:43:11 PM PDT 24 |
9921664600 ps |
| T1092 |
/workspace/coverage/default/12.flash_ctrl_mp_regions.3852234688 |
|
|
Jun 30 05:38:14 PM PDT 24 |
Jun 30 05:47:16 PM PDT 24 |
35764826600 ps |
| T1093 |
/workspace/coverage/default/33.flash_ctrl_smoke.1917415729 |
|
|
Jun 30 05:41:09 PM PDT 24 |
Jun 30 05:42:27 PM PDT 24 |
18528000 ps |
| T1094 |
/workspace/coverage/default/12.flash_ctrl_intr_rd.1765071333 |
|
|
Jun 30 05:38:15 PM PDT 24 |
Jun 30 05:40:41 PM PDT 24 |
2529223400 ps |
| T1095 |
/workspace/coverage/default/14.flash_ctrl_connect.191794752 |
|
|
Jun 30 05:38:34 PM PDT 24 |
Jun 30 05:38:48 PM PDT 24 |
25959700 ps |
| T1096 |
/workspace/coverage/default/14.flash_ctrl_alert_test.1248032606 |
|
|
Jun 30 05:38:42 PM PDT 24 |
Jun 30 05:38:57 PM PDT 24 |
153320000 ps |
| T1097 |
/workspace/coverage/default/12.flash_ctrl_phy_arb.1969831220 |
|
|
Jun 30 05:38:06 PM PDT 24 |
Jun 30 05:45:15 PM PDT 24 |
3005968600 ps |
| T1098 |
/workspace/coverage/default/10.flash_ctrl_connect.430479171 |
|
|
Jun 30 05:37:48 PM PDT 24 |
Jun 30 05:38:02 PM PDT 24 |
32455500 ps |
| T1099 |
/workspace/coverage/default/47.flash_ctrl_sec_info_access.1019595982 |
|
|
Jun 30 05:42:10 PM PDT 24 |
Jun 30 05:43:27 PM PDT 24 |
1603066400 ps |
| T1100 |
/workspace/coverage/default/39.flash_ctrl_sec_info_access.2685838882 |
|
|
Jun 30 05:41:45 PM PDT 24 |
Jun 30 05:43:03 PM PDT 24 |
5882233500 ps |
| T1101 |
/workspace/coverage/default/36.flash_ctrl_alert_test.1792530997 |
|
|
Jun 30 05:41:32 PM PDT 24 |
Jun 30 05:41:47 PM PDT 24 |
107864700 ps |
| T1102 |
/workspace/coverage/default/41.flash_ctrl_sec_info_access.1922697017 |
|
|
Jun 30 05:41:53 PM PDT 24 |
Jun 30 05:42:58 PM PDT 24 |
1009487900 ps |
| T1103 |
/workspace/coverage/default/4.flash_ctrl_otp_reset.2666559752 |
|
|
Jun 30 05:35:49 PM PDT 24 |
Jun 30 05:37:42 PM PDT 24 |
317855100 ps |
| T1104 |
/workspace/coverage/default/12.flash_ctrl_disable.3706442238 |
|
|
Jun 30 05:38:14 PM PDT 24 |
Jun 30 05:38:37 PM PDT 24 |
15728900 ps |
| T227 |
/workspace/coverage/default/2.flash_ctrl_wr_intg.3404018879 |
|
|
Jun 30 05:35:05 PM PDT 24 |
Jun 30 05:35:21 PM PDT 24 |
84833100 ps |
| T1105 |
/workspace/coverage/default/78.flash_ctrl_connect.2385460139 |
|
|
Jun 30 05:42:36 PM PDT 24 |
Jun 30 05:42:53 PM PDT 24 |
15240800 ps |
| T1106 |
/workspace/coverage/default/2.flash_ctrl_intr_wr_slow_flash.3668744575 |
|
|
Jun 30 05:34:57 PM PDT 24 |
Jun 30 05:37:36 PM PDT 24 |
44563401000 ps |
| T1107 |
/workspace/coverage/default/28.flash_ctrl_smoke.4110320137 |
|
|
Jun 30 05:40:43 PM PDT 24 |
Jun 30 05:43:10 PM PDT 24 |
24791400 ps |
| T1108 |
/workspace/coverage/default/0.flash_ctrl_rw_derr.2879720245 |
|
|
Jun 30 05:34:22 PM PDT 24 |
Jun 30 05:45:00 PM PDT 24 |
5537889600 ps |
| T1109 |
/workspace/coverage/default/43.flash_ctrl_disable.4239108819 |
|
|
Jun 30 05:41:59 PM PDT 24 |
Jun 30 05:42:22 PM PDT 24 |
33376600 ps |
| T1110 |
/workspace/coverage/default/29.flash_ctrl_otp_reset.755139179 |
|
|
Jun 30 05:40:50 PM PDT 24 |
Jun 30 05:43:05 PM PDT 24 |
102758900 ps |
| T263 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.3604684638 |
|
|
Jun 30 05:27:05 PM PDT 24 |
Jun 30 05:27:19 PM PDT 24 |
56227800 ps |
| T1111 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2769810807 |
|
|
Jun 30 05:26:40 PM PDT 24 |
Jun 30 05:26:58 PM PDT 24 |
29283000 ps |
| T264 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.468874989 |
|
|
Jun 30 05:26:53 PM PDT 24 |
Jun 30 05:27:08 PM PDT 24 |
31311200 ps |
| T99 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.442308640 |
|
|
Jun 30 05:26:45 PM PDT 24 |
Jun 30 05:27:01 PM PDT 24 |
41852800 ps |
| T1112 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.120560959 |
|
|
Jun 30 05:26:20 PM PDT 24 |
Jun 30 05:26:33 PM PDT 24 |
44108000 ps |
| T100 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.3050318190 |
|
|
Jun 30 05:26:29 PM PDT 24 |
Jun 30 05:26:46 PM PDT 24 |
36861600 ps |
| T1113 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.1062102533 |
|
|
Jun 30 05:26:36 PM PDT 24 |
Jun 30 05:26:50 PM PDT 24 |
76136900 ps |
| T63 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.1839493343 |
|
|
Jun 30 05:26:36 PM PDT 24 |
Jun 30 05:34:20 PM PDT 24 |
2365757000 ps |
| T64 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.773924254 |
|
|
Jun 30 05:26:31 PM PDT 24 |
Jun 30 05:33:04 PM PDT 24 |
179669400 ps |
| T265 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.3329106294 |
|
|
Jun 30 05:27:01 PM PDT 24 |
Jun 30 05:27:15 PM PDT 24 |
52174600 ps |
| T1114 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3217668575 |
|
|
Jun 30 05:26:32 PM PDT 24 |
Jun 30 05:26:49 PM PDT 24 |
88325000 ps |
| T215 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1720162929 |
|
|
Jun 30 05:26:15 PM PDT 24 |
Jun 30 05:26:32 PM PDT 24 |
61692200 ps |
| T65 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1885855649 |
|
|
Jun 30 05:26:33 PM PDT 24 |
Jun 30 05:26:51 PM PDT 24 |
125446300 ps |
| T254 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.2517440933 |
|
|
Jun 30 05:26:41 PM PDT 24 |
Jun 30 05:27:12 PM PDT 24 |
237536700 ps |
| T216 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.4002961331 |
|
|
Jun 30 05:26:15 PM PDT 24 |
Jun 30 05:41:57 PM PDT 24 |
16944245200 ps |
| T233 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2080637408 |
|
|
Jun 30 05:26:34 PM PDT 24 |
Jun 30 05:41:24 PM PDT 24 |
3218859600 ps |
| T338 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.3674260606 |
|
|
Jun 30 05:26:14 PM PDT 24 |
Jun 30 05:27:21 PM PDT 24 |
634463600 ps |
| T267 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3525459093 |
|
|
Jun 30 05:26:23 PM PDT 24 |
Jun 30 05:26:50 PM PDT 24 |
30569300 ps |
| T234 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.3362666157 |
|
|
Jun 30 05:26:34 PM PDT 24 |
Jun 30 05:41:50 PM PDT 24 |
653785300 ps |
| T255 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.887887767 |
|
|
Jun 30 05:26:16 PM PDT 24 |
Jun 30 05:26:51 PM PDT 24 |
783107000 ps |
| T339 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3808073822 |
|
|
Jun 30 05:27:05 PM PDT 24 |
Jun 30 05:27:19 PM PDT 24 |
66155500 ps |
| T235 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3474895412 |
|
|
Jun 30 05:26:43 PM PDT 24 |
Jun 30 05:27:00 PM PDT 24 |
45935200 ps |
| T340 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.587261741 |
|
|
Jun 30 05:27:06 PM PDT 24 |
Jun 30 05:27:20 PM PDT 24 |
26727700 ps |
| T1115 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3190040682 |
|
|
Jun 30 05:26:28 PM PDT 24 |
Jun 30 05:26:42 PM PDT 24 |
53533100 ps |
| T236 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2684094003 |
|
|
Jun 30 05:26:17 PM PDT 24 |
Jun 30 05:26:37 PM PDT 24 |
56905200 ps |
| T1116 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.3888333626 |
|
|
Jun 30 05:26:44 PM PDT 24 |
Jun 30 05:27:00 PM PDT 24 |
11501200 ps |
| T237 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3196156133 |
|
|
Jun 30 05:26:33 PM PDT 24 |
Jun 30 05:26:54 PM PDT 24 |
63214300 ps |
| T256 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.793406493 |
|
|
Jun 30 05:26:42 PM PDT 24 |
Jun 30 05:27:01 PM PDT 24 |
409370800 ps |
| T341 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.1938626402 |
|
|
Jun 30 05:26:31 PM PDT 24 |
Jun 30 05:26:46 PM PDT 24 |
17389700 ps |
| T1117 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2497748217 |
|
|
Jun 30 05:26:17 PM PDT 24 |
Jun 30 05:26:49 PM PDT 24 |
19720500 ps |
| T343 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.2102327495 |
|
|
Jun 30 05:26:53 PM PDT 24 |
Jun 30 05:27:08 PM PDT 24 |
18045600 ps |
| T1118 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.391660012 |
|
|
Jun 30 05:26:44 PM PDT 24 |
Jun 30 05:26:59 PM PDT 24 |
17228000 ps |
| T1119 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.4108599898 |
|
|
Jun 30 05:26:31 PM PDT 24 |
Jun 30 05:26:49 PM PDT 24 |
11490200 ps |
| T238 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1634381167 |
|
|
Jun 30 05:26:40 PM PDT 24 |
Jun 30 05:26:58 PM PDT 24 |
196063900 ps |
| T342 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.1837048021 |
|
|
Jun 30 05:26:32 PM PDT 24 |
Jun 30 05:26:46 PM PDT 24 |
33178100 ps |
| T1120 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1383298126 |
|
|
Jun 30 05:26:16 PM PDT 24 |
Jun 30 05:26:33 PM PDT 24 |
113675000 ps |
| T257 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.4233402632 |
|
|
Jun 30 05:26:40 PM PDT 24 |
Jun 30 05:27:15 PM PDT 24 |
121983600 ps |
| T239 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3814238865 |
|
|
Jun 30 05:26:14 PM PDT 24 |
Jun 30 05:26:35 PM PDT 24 |
234787300 ps |
| T258 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.193820353 |
|
|
Jun 30 05:26:31 PM PDT 24 |
Jun 30 05:26:49 PM PDT 24 |
28765600 ps |
| T259 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.3099370861 |
|
|
Jun 30 05:26:51 PM PDT 24 |
Jun 30 05:27:29 PM PDT 24 |
391470100 ps |
| T344 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.2918740278 |
|
|
Jun 30 05:27:05 PM PDT 24 |
Jun 30 05:27:19 PM PDT 24 |
29712500 ps |
| T260 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.3403632371 |
|
|
Jun 30 05:26:36 PM PDT 24 |
Jun 30 05:27:06 PM PDT 24 |
597753200 ps |
| T364 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.2656424051 |
|
|
Jun 30 05:26:17 PM PDT 24 |
Jun 30 05:41:19 PM PDT 24 |
337083600 ps |
| T345 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.4134219575 |
|
|
Jun 30 05:27:12 PM PDT 24 |
Jun 30 05:27:26 PM PDT 24 |
31395300 ps |
| T1121 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.173776189 |
|
|
Jun 30 05:26:22 PM PDT 24 |
Jun 30 05:26:38 PM PDT 24 |
24746800 ps |
| T242 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1122886333 |
|
|
Jun 30 05:26:17 PM PDT 24 |
Jun 30 05:26:31 PM PDT 24 |
59343600 ps |
| T273 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3153942941 |
|
|
Jun 30 05:26:44 PM PDT 24 |
Jun 30 05:27:04 PM PDT 24 |
99462500 ps |
| T1122 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.1698703594 |
|
|
Jun 30 05:26:37 PM PDT 24 |
Jun 30 05:26:50 PM PDT 24 |
21054600 ps |
| T1123 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.2323744175 |
|
|
Jun 30 05:26:51 PM PDT 24 |
Jun 30 05:27:06 PM PDT 24 |
127406500 ps |
| T272 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.1167516113 |
|
|
Jun 30 05:26:41 PM PDT 24 |
Jun 30 05:41:48 PM PDT 24 |
805750200 ps |
| T1124 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.2618759451 |
|
|
Jun 30 05:26:29 PM PDT 24 |
Jun 30 05:26:45 PM PDT 24 |
19877600 ps |
| T1125 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1228728503 |
|
|
Jun 30 05:26:30 PM PDT 24 |
Jun 30 05:27:05 PM PDT 24 |
1039258700 ps |
| T337 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2951351240 |
|
|
Jun 30 05:26:10 PM PDT 24 |
Jun 30 05:41:13 PM PDT 24 |
883899600 ps |
| T1126 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.2738035900 |
|
|
Jun 30 05:26:30 PM PDT 24 |
Jun 30 05:26:51 PM PDT 24 |
191934300 ps |
| T1127 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.937662215 |
|
|
Jun 30 05:26:38 PM PDT 24 |
Jun 30 05:26:55 PM PDT 24 |
12538600 ps |
| T310 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.4017161447 |
|
|
Jun 30 05:26:40 PM PDT 24 |
Jun 30 05:26:59 PM PDT 24 |
242487300 ps |
| T1128 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.47196370 |
|
|
Jun 30 05:26:46 PM PDT 24 |
Jun 30 05:27:02 PM PDT 24 |
15297700 ps |
| T1129 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.3283611003 |
|
|
Jun 30 05:26:33 PM PDT 24 |
Jun 30 05:26:49 PM PDT 24 |
11711500 ps |
| T274 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3304375837 |
|
|
Jun 30 05:26:38 PM PDT 24 |
Jun 30 05:39:19 PM PDT 24 |
5800751600 ps |
| T1130 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2872806997 |
|
|
Jun 30 05:26:33 PM PDT 24 |
Jun 30 05:26:48 PM PDT 24 |
275258500 ps |
| T1131 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.1922199713 |
|
|
Jun 30 05:26:53 PM PDT 24 |
Jun 30 05:27:07 PM PDT 24 |
18017900 ps |
| T262 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.736511947 |
|
|
Jun 30 05:26:51 PM PDT 24 |
Jun 30 05:27:14 PM PDT 24 |
109845600 ps |
| T346 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.3336847029 |
|
|
Jun 30 05:26:32 PM PDT 24 |
Jun 30 05:26:46 PM PDT 24 |
54393200 ps |
| T1132 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2307007560 |
|
|
Jun 30 05:26:52 PM PDT 24 |
Jun 30 05:27:07 PM PDT 24 |
32258600 ps |
| T1133 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1806915364 |
|
|
Jun 30 05:26:43 PM PDT 24 |
Jun 30 05:26:57 PM PDT 24 |
15252900 ps |
| T1134 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.900823746 |
|
|
Jun 30 05:26:38 PM PDT 24 |
Jun 30 05:26:54 PM PDT 24 |
29379000 ps |
| T1135 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.3802457578 |
|
|
Jun 30 05:26:23 PM PDT 24 |
Jun 30 05:26:37 PM PDT 24 |
45798200 ps |
| T1136 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3600274587 |
|
|
Jun 30 05:26:18 PM PDT 24 |
Jun 30 05:27:10 PM PDT 24 |
798066700 ps |
| T1137 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3733673561 |
|
|
Jun 30 05:26:59 PM PDT 24 |
Jun 30 05:27:13 PM PDT 24 |
27923600 ps |
| T1138 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.389195090 |
|
|
Jun 30 05:26:33 PM PDT 24 |
Jun 30 05:27:05 PM PDT 24 |
32904000 ps |
| T1139 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.1958726313 |
|
|
Jun 30 05:26:44 PM PDT 24 |
Jun 30 05:27:03 PM PDT 24 |
969217200 ps |
| T1140 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1541521735 |
|
|
Jun 30 05:26:50 PM PDT 24 |
Jun 30 05:27:09 PM PDT 24 |
297638200 ps |
| T1141 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1669192389 |
|
|
Jun 30 05:26:49 PM PDT 24 |
Jun 30 05:27:10 PM PDT 24 |
122405400 ps |
| T1142 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2082265583 |
|
|
Jun 30 05:26:21 PM PDT 24 |
Jun 30 05:26:43 PM PDT 24 |
3096281000 ps |
| T1143 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3189991098 |
|
|
Jun 30 05:26:07 PM PDT 24 |
Jun 30 05:26:25 PM PDT 24 |
39581600 ps |
| T360 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.3597735473 |
|
|
Jun 30 05:26:15 PM PDT 24 |
Jun 30 05:26:29 PM PDT 24 |
16535700 ps |
| T1144 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1173564537 |
|
|
Jun 30 05:26:30 PM PDT 24 |
Jun 30 05:27:26 PM PDT 24 |
1772021800 ps |
| T1145 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.3082364847 |
|
|
Jun 30 05:26:53 PM PDT 24 |
Jun 30 05:27:08 PM PDT 24 |
14463700 ps |
| T1146 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.956766443 |
|
|
Jun 30 05:26:40 PM PDT 24 |
Jun 30 05:26:59 PM PDT 24 |
26839200 ps |
| T1147 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.1511129932 |
|
|
Jun 30 05:26:51 PM PDT 24 |
Jun 30 05:27:06 PM PDT 24 |
15342600 ps |
| T1148 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.2011141894 |
|
|
Jun 30 05:26:17 PM PDT 24 |
Jun 30 05:26:34 PM PDT 24 |
76364600 ps |
| T275 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.264519979 |
|
|
Jun 30 05:26:50 PM PDT 24 |
Jun 30 05:39:30 PM PDT 24 |
334609300 ps |
| T1149 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.508254210 |
|
|
Jun 30 05:26:58 PM PDT 24 |
Jun 30 05:27:12 PM PDT 24 |
63941500 ps |
| T1150 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.3046916329 |
|
|
Jun 30 05:26:51 PM PDT 24 |
Jun 30 05:27:05 PM PDT 24 |
17525700 ps |
| T268 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.614670392 |
|
|
Jun 30 05:26:37 PM PDT 24 |
Jun 30 05:26:58 PM PDT 24 |
114096500 ps |
| T1151 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2900589136 |
|
|
Jun 30 05:26:40 PM PDT 24 |
Jun 30 05:26:58 PM PDT 24 |
45289500 ps |
| T1152 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.353991094 |
|
|
Jun 30 05:26:43 PM PDT 24 |
Jun 30 05:27:03 PM PDT 24 |
208894800 ps |
| T1153 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.663811879 |
|
|
Jun 30 05:27:12 PM PDT 24 |
Jun 30 05:27:27 PM PDT 24 |
15088700 ps |
| T1154 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.3720008282 |
|
|
Jun 30 05:27:04 PM PDT 24 |
Jun 30 05:27:18 PM PDT 24 |
15803700 ps |
| T243 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2251383778 |
|
|
Jun 30 05:26:18 PM PDT 24 |
Jun 30 05:26:33 PM PDT 24 |
17474900 ps |
| T1155 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2140068146 |
|
|
Jun 30 05:26:44 PM PDT 24 |
Jun 30 05:27:00 PM PDT 24 |
14011100 ps |
| T1156 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.280773230 |
|
|
Jun 30 05:26:16 PM PDT 24 |
Jun 30 05:26:35 PM PDT 24 |
56219600 ps |
| T1157 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.3553260721 |
|
|
Jun 30 05:26:09 PM PDT 24 |
Jun 30 05:26:25 PM PDT 24 |
13919200 ps |
| T1158 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.78432424 |
|
|
Jun 30 05:26:20 PM PDT 24 |
Jun 30 05:26:37 PM PDT 24 |
21984600 ps |
| T1159 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2996929624 |
|
|
Jun 30 05:26:45 PM PDT 24 |
Jun 30 05:27:00 PM PDT 24 |
329924100 ps |
| T1160 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.101416 |
|
|
Jun 30 05:26:59 PM PDT 24 |
Jun 30 05:27:13 PM PDT 24 |
90274800 ps |
| T1161 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.3818941272 |
|
|
Jun 30 05:26:44 PM PDT 24 |
Jun 30 05:26:58 PM PDT 24 |
44639900 ps |
| T1162 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.2234791445 |
|
|
Jun 30 05:26:16 PM PDT 24 |
Jun 30 05:26:33 PM PDT 24 |
44578100 ps |
| T311 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.658825108 |
|
|
Jun 30 05:26:44 PM PDT 24 |
Jun 30 05:27:03 PM PDT 24 |
955274000 ps |
| T1163 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.3689303646 |
|
|
Jun 30 05:26:20 PM PDT 24 |
Jun 30 05:26:37 PM PDT 24 |
114121100 ps |
| T1164 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.2536834858 |
|
|
Jun 30 05:26:51 PM PDT 24 |
Jun 30 05:27:06 PM PDT 24 |
54843500 ps |
| T1165 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.254540582 |
|
|
Jun 30 05:27:03 PM PDT 24 |
Jun 30 05:27:18 PM PDT 24 |
34979700 ps |
| T271 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.2443371385 |
|
|
Jun 30 05:26:36 PM PDT 24 |
Jun 30 05:26:55 PM PDT 24 |
203849600 ps |
| T1166 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.1821788985 |
|
|
Jun 30 05:26:45 PM PDT 24 |
Jun 30 05:26:58 PM PDT 24 |
15336600 ps |
| T1167 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.568116468 |
|
|
Jun 30 05:27:13 PM PDT 24 |
Jun 30 05:27:28 PM PDT 24 |
58762400 ps |
| T266 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.3913421638 |
|
|
Jun 30 05:26:41 PM PDT 24 |
Jun 30 05:27:03 PM PDT 24 |
229517100 ps |
| T1168 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1852499245 |
|
|
Jun 30 05:26:33 PM PDT 24 |
Jun 30 05:26:52 PM PDT 24 |
139098300 ps |
| T1169 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.170187564 |
|
|
Jun 30 05:27:11 PM PDT 24 |
Jun 30 05:27:25 PM PDT 24 |
43582300 ps |
| T1170 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.3264796551 |
|
|
Jun 30 05:26:16 PM PDT 24 |
Jun 30 05:26:32 PM PDT 24 |
41491500 ps |
| T1171 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.4010409575 |
|
|
Jun 30 05:26:30 PM PDT 24 |
Jun 30 05:26:46 PM PDT 24 |
30166600 ps |
| T244 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.3870972181 |
|
|
Jun 30 05:26:14 PM PDT 24 |
Jun 30 05:26:28 PM PDT 24 |
29468000 ps |
| T1172 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.2216659492 |
|
|
Jun 30 05:26:52 PM PDT 24 |
Jun 30 05:27:07 PM PDT 24 |
52719700 ps |
| T1173 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.2392364772 |
|
|
Jun 30 05:26:32 PM PDT 24 |
Jun 30 05:26:49 PM PDT 24 |
36987700 ps |
| T1174 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.1319414331 |
|
|
Jun 30 05:26:40 PM PDT 24 |
Jun 30 05:26:55 PM PDT 24 |
26700600 ps |
| T1175 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.1202147661 |
|
|
Jun 30 05:26:40 PM PDT 24 |
Jun 30 05:26:56 PM PDT 24 |
35610200 ps |
| T1176 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.3007741303 |
|
|
Jun 30 05:26:53 PM PDT 24 |
Jun 30 05:27:08 PM PDT 24 |
214479700 ps |
| T1177 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.382656919 |
|
|
Jun 30 05:26:38 PM PDT 24 |
Jun 30 05:26:56 PM PDT 24 |
25940800 ps |
| T1178 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2822210538 |
|
|
Jun 30 05:26:41 PM PDT 24 |
Jun 30 05:26:58 PM PDT 24 |
54296200 ps |
| T1179 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.2545475524 |
|
|
Jun 30 05:26:15 PM PDT 24 |
Jun 30 05:26:48 PM PDT 24 |
2739915900 ps |
| T1180 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2896052290 |
|
|
Jun 30 05:26:52 PM PDT 24 |
Jun 30 05:27:07 PM PDT 24 |
59224500 ps |
| T1181 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.408246314 |
|
|
Jun 30 05:26:55 PM PDT 24 |
Jun 30 05:27:09 PM PDT 24 |
60803200 ps |
| T312 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.862574587 |
|
|
Jun 30 05:26:15 PM PDT 24 |
Jun 30 05:26:47 PM PDT 24 |
118479300 ps |
| T365 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.3756364576 |
|
|
Jun 30 05:26:38 PM PDT 24 |
Jun 30 05:34:17 PM PDT 24 |
427419500 ps |
| T1182 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.2025351595 |
|
|
Jun 30 05:26:46 PM PDT 24 |
Jun 30 05:27:00 PM PDT 24 |
40828900 ps |
| T1183 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.1448883834 |
|
|
Jun 30 05:26:59 PM PDT 24 |
Jun 30 05:27:34 PM PDT 24 |
67361500 ps |
| T1184 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.810954199 |
|
|
Jun 30 05:26:52 PM PDT 24 |
Jun 30 05:27:07 PM PDT 24 |
26007000 ps |
| T1185 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.724963912 |
|
|
Jun 30 05:26:15 PM PDT 24 |
Jun 30 05:26:29 PM PDT 24 |
35452100 ps |
| T1186 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.751653692 |
|
|
Jun 30 05:26:23 PM PDT 24 |
Jun 30 05:26:37 PM PDT 24 |
23941200 ps |
| T362 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.1404750771 |
|
|
Jun 30 05:26:29 PM PDT 24 |
Jun 30 05:39:03 PM PDT 24 |
1386543700 ps |
| T270 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.4012975448 |
|
|
Jun 30 05:26:09 PM PDT 24 |
Jun 30 05:26:29 PM PDT 24 |
47094600 ps |
| T1187 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.1073889130 |
|
|
Jun 30 05:26:30 PM PDT 24 |
Jun 30 05:26:46 PM PDT 24 |
19045400 ps |
| T1188 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.566812741 |
|
|
Jun 30 05:26:39 PM PDT 24 |
Jun 30 05:26:53 PM PDT 24 |
23485600 ps |
| T1189 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.414587184 |
|
|
Jun 30 05:26:31 PM PDT 24 |
Jun 30 05:26:50 PM PDT 24 |
47561100 ps |
| T1190 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.2555780151 |
|
|
Jun 30 05:26:31 PM PDT 24 |
Jun 30 05:26:52 PM PDT 24 |
96643300 ps |
| T1191 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2699629231 |
|
|
Jun 30 05:26:45 PM PDT 24 |
Jun 30 05:26:59 PM PDT 24 |
17909000 ps |
| T1192 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.2398325846 |
|
|
Jun 30 05:26:16 PM PDT 24 |
Jun 30 05:26:33 PM PDT 24 |
365953900 ps |
| T1193 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.3787039217 |
|
|
Jun 30 05:26:56 PM PDT 24 |
Jun 30 05:27:14 PM PDT 24 |
51487900 ps |
| T1194 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2727883638 |
|
|
Jun 30 05:26:17 PM PDT 24 |
Jun 30 05:27:25 PM PDT 24 |
661616100 ps |
| T1195 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3686245924 |
|
|
Jun 30 05:26:18 PM PDT 24 |
Jun 30 05:27:13 PM PDT 24 |
10339152700 ps |
| T1196 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2715124193 |
|
|
Jun 30 05:26:30 PM PDT 24 |
Jun 30 05:26:47 PM PDT 24 |
19505500 ps |
| T1197 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2492996305 |
|
|
Jun 30 05:26:38 PM PDT 24 |
Jun 30 05:26:55 PM PDT 24 |
202133800 ps |
| T1198 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.673559808 |
|
|
Jun 30 05:27:05 PM PDT 24 |
Jun 30 05:27:18 PM PDT 24 |
57450900 ps |
| T1199 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3456790388 |
|
|
Jun 30 05:26:40 PM PDT 24 |
Jun 30 05:27:00 PM PDT 24 |
201809800 ps |
| T1200 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2564065000 |
|
|
Jun 30 05:26:40 PM PDT 24 |
Jun 30 05:26:58 PM PDT 24 |
18974700 ps |
| T1201 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.3325582639 |
|
|
Jun 30 05:26:47 PM PDT 24 |
Jun 30 05:27:05 PM PDT 24 |
481371000 ps |
| T1202 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.332566233 |
|
|
Jun 30 05:26:55 PM PDT 24 |
Jun 30 05:27:09 PM PDT 24 |
31467100 ps |
| T269 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1372610176 |
|
|
Jun 30 05:26:39 PM PDT 24 |
Jun 30 05:27:00 PM PDT 24 |
124021900 ps |
| T313 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1539691026 |
|
|
Jun 30 05:26:51 PM PDT 24 |
Jun 30 05:27:10 PM PDT 24 |
98131400 ps |
| T1203 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.4269549229 |
|
|
Jun 30 05:26:30 PM PDT 24 |
Jun 30 05:27:06 PM PDT 24 |
983183700 ps |
| T314 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.2976750756 |
|
|
Jun 30 05:26:16 PM PDT 24 |
Jun 30 05:27:21 PM PDT 24 |
1572399200 ps |
| T1204 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.1842445980 |
|
|
Jun 30 05:26:36 PM PDT 24 |
Jun 30 05:26:53 PM PDT 24 |
320575300 ps |
| T363 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.1210497539 |
|
|
Jun 30 05:26:33 PM PDT 24 |
Jun 30 05:41:40 PM PDT 24 |
689528900 ps |
| T1205 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3438070199 |
|
|
Jun 30 05:26:47 PM PDT 24 |
Jun 30 05:27:08 PM PDT 24 |
116330800 ps |
| T1206 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.3076124531 |
|
|
Jun 30 05:26:50 PM PDT 24 |
Jun 30 05:27:09 PM PDT 24 |
174180800 ps |
| T1207 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.3653934137 |
|
|
Jun 30 05:26:31 PM PDT 24 |
Jun 30 05:26:50 PM PDT 24 |
36988900 ps |
| T1208 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2851211626 |
|
|
Jun 30 05:26:16 PM PDT 24 |
Jun 30 05:27:37 PM PDT 24 |
15439375800 ps |
| T1209 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2610502165 |
|
|
Jun 30 05:26:19 PM PDT 24 |
Jun 30 05:27:12 PM PDT 24 |
449092300 ps |
| T1210 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.164442355 |
|
|
Jun 30 05:26:38 PM PDT 24 |
Jun 30 05:26:55 PM PDT 24 |
41285500 ps |
| T368 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3897542597 |
|
|
Jun 30 05:26:56 PM PDT 24 |
Jun 30 05:42:08 PM PDT 24 |
696682000 ps |
| T1211 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.539093192 |
|
|
Jun 30 05:26:41 PM PDT 24 |
Jun 30 05:26:56 PM PDT 24 |
104168100 ps |
| T1212 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3076345110 |
|
|
Jun 30 05:27:04 PM PDT 24 |
Jun 30 05:27:18 PM PDT 24 |
16623000 ps |
| T1213 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.813690397 |
|
|
Jun 30 05:26:31 PM PDT 24 |
Jun 30 05:26:50 PM PDT 24 |
138729600 ps |
| T1214 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.3025047096 |
|
|
Jun 30 05:26:49 PM PDT 24 |
Jun 30 05:27:04 PM PDT 24 |
30973400 ps |
| T1215 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.321758785 |
|
|
Jun 30 05:26:58 PM PDT 24 |
Jun 30 05:27:11 PM PDT 24 |
27761400 ps |
| T1216 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1738973412 |
|
|
Jun 30 05:26:15 PM PDT 24 |
Jun 30 05:26:42 PM PDT 24 |
18790400 ps |
| T367 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.2397253074 |
|
|
Jun 30 05:26:19 PM PDT 24 |
Jun 30 05:41:16 PM PDT 24 |
1383520100 ps |
| T1217 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1709792685 |
|
|
Jun 30 05:26:16 PM PDT 24 |
Jun 30 05:27:31 PM PDT 24 |
2737418700 ps |
| T1218 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3720883703 |
|
|
Jun 30 05:26:31 PM PDT 24 |
Jun 30 05:27:59 PM PDT 24 |
13543501500 ps |
| T1219 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1891829407 |
|
|
Jun 30 05:26:45 PM PDT 24 |
Jun 30 05:27:03 PM PDT 24 |
72979100 ps |
| T245 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.3739910751 |
|
|
Jun 30 05:26:37 PM PDT 24 |
Jun 30 05:26:51 PM PDT 24 |
34015000 ps |
| T366 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.632729985 |
|
|
Jun 30 05:26:38 PM PDT 24 |
Jun 30 05:34:20 PM PDT 24 |
456068200 ps |
| T315 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.1462708434 |
|
|
Jun 30 05:26:33 PM PDT 24 |
Jun 30 05:26:53 PM PDT 24 |
194523600 ps |
| T361 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3844768715 |
|
|
Jun 30 05:26:38 PM PDT 24 |
Jun 30 05:26:59 PM PDT 24 |
158646100 ps |
| T1220 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.3759403225 |
|
|
Jun 30 05:26:30 PM PDT 24 |
Jun 30 05:26:49 PM PDT 24 |
38302800 ps |
| T1221 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.1793182003 |
|
|
Jun 30 05:26:38 PM PDT 24 |
Jun 30 05:26:58 PM PDT 24 |
366035400 ps |
| T1222 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.330605352 |
|
|
Jun 30 05:26:37 PM PDT 24 |
Jun 30 05:26:52 PM PDT 24 |
17281200 ps |
| T1223 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3364323181 |
|
|
Jun 30 05:26:44 PM PDT 24 |
Jun 30 05:33:13 PM PDT 24 |
178252000 ps |
| T1224 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.2941906961 |
|
|
Jun 30 05:26:19 PM PDT 24 |
Jun 30 05:26:35 PM PDT 24 |
35698600 ps |
| T1225 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.951922135 |
|
|
Jun 30 05:26:50 PM PDT 24 |
Jun 30 05:39:40 PM PDT 24 |
753568600 ps |
| T246 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1589509180 |
|
|
Jun 30 05:26:23 PM PDT 24 |
Jun 30 05:26:37 PM PDT 24 |
28504200 ps |
| T1226 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.1367752305 |
|
|
Jun 30 05:26:38 PM PDT 24 |
Jun 30 05:26:55 PM PDT 24 |
13507000 ps |
| T1227 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.4037466459 |
|
|
Jun 30 05:26:15 PM PDT 24 |
Jun 30 05:26:35 PM PDT 24 |
95955800 ps |
| T1228 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.853792292 |
|
|
Jun 30 05:26:35 PM PDT 24 |
Jun 30 05:26:49 PM PDT 24 |
47615000 ps |
| T1229 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3516300836 |
|
|
Jun 30 05:26:52 PM PDT 24 |
Jun 30 05:27:06 PM PDT 24 |
12943000 ps |
| T1230 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.3555908025 |
|
|
Jun 30 05:26:46 PM PDT 24 |
Jun 30 05:27:04 PM PDT 24 |
349728400 ps |
| T1231 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.2045305544 |
|
|
Jun 30 05:26:36 PM PDT 24 |
Jun 30 05:26:50 PM PDT 24 |
150748400 ps |
| T1232 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.1427551701 |
|
|
Jun 30 05:26:32 PM PDT 24 |
Jun 30 05:26:50 PM PDT 24 |
68474100 ps |
| T1233 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.644175624 |
|
|
Jun 30 05:26:17 PM PDT 24 |
Jun 30 05:26:31 PM PDT 24 |
48431300 ps |
| T1234 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.4146284098 |
|
|
Jun 30 05:26:15 PM PDT 24 |
Jun 30 05:26:51 PM PDT 24 |
885931400 ps |
| T1235 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.2276523373 |
|
|
Jun 30 05:26:10 PM PDT 24 |
Jun 30 05:26:25 PM PDT 24 |
81725700 ps |
| T1236 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1988513825 |
|
|
Jun 30 05:26:40 PM PDT 24 |
Jun 30 05:27:05 PM PDT 24 |
1696494300 ps |
| T1237 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.2406036867 |
|
|
Jun 30 05:26:49 PM PDT 24 |
Jun 30 05:27:04 PM PDT 24 |
17287600 ps |
| T1238 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.2427475365 |
|
|
Jun 30 05:26:45 PM PDT 24 |
Jun 30 05:27:03 PM PDT 24 |
178067000 ps |
| T1239 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2842818063 |
|
|
Jun 30 05:27:06 PM PDT 24 |
Jun 30 05:27:19 PM PDT 24 |
20001600 ps |
| T1240 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2619262715 |
|
|
Jun 30 05:26:20 PM PDT 24 |
Jun 30 05:26:37 PM PDT 24 |
24679700 ps |
| T1241 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.3719829763 |
|
|
Jun 30 05:26:49 PM PDT 24 |
Jun 30 05:27:05 PM PDT 24 |
13907900 ps |
| T1242 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.2392540648 |
|
|
Jun 30 05:26:37 PM PDT 24 |
Jun 30 05:26:53 PM PDT 24 |
161982200 ps |
| T1243 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.303854556 |
|
|
Jun 30 05:26:39 PM PDT 24 |
Jun 30 05:26:59 PM PDT 24 |
68711400 ps |
| T1244 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.948681830 |
|
|
Jun 30 05:26:07 PM PDT 24 |
Jun 30 05:26:22 PM PDT 24 |
27650900 ps |
| T276 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1027664945 |
|
|
Jun 30 05:26:39 PM PDT 24 |
Jun 30 05:41:59 PM PDT 24 |
3387485800 ps |
| T1245 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.2765158792 |
|
|
Jun 30 05:26:16 PM PDT 24 |
Jun 30 05:26:37 PM PDT 24 |
258886200 ps |
| T1246 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2081581078 |
|
|
Jun 30 05:26:39 PM PDT 24 |
Jun 30 05:26:57 PM PDT 24 |
32043800 ps |
| T1247 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.2271701792 |
|
|
Jun 30 05:26:41 PM PDT 24 |
Jun 30 05:26:56 PM PDT 24 |
18103000 ps |
| T1248 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.445479118 |
|
|
Jun 30 05:26:41 PM PDT 24 |
Jun 30 05:26:57 PM PDT 24 |
46479100 ps |
| T1249 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1683338113 |
|
|
Jun 30 05:26:40 PM PDT 24 |
Jun 30 05:26:57 PM PDT 24 |
90956000 ps |
| T1250 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.298872821 |
|
|
Jun 30 05:26:16 PM PDT 24 |
Jun 30 05:26:30 PM PDT 24 |
144454300 ps |