Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	319077	1		T1	1		T2	2		T3	1
all_values[1]	319077	1		T1	1		T2	2		T3	1
all_values[2]	319077	1		T1	1		T2	2		T3	1
all_values[3]	319077	1		T1	1		T2	2		T3	1
all_values[4]	319077	1		T1	1		T2	2		T3	1
all_values[5]	319077	1		T1	1		T2	2		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	644312	1		T1	6		T2	12		T3	6
auto[1]	1270150	1		T6	13136		T7	36608		T28	3564

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	939641	1		T1	4		T2	6		T3	4
auto[1]	974821	1		T1	2		T2	6		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	318913	1		T1	1		T2	2		T3	1
all_values[0]	auto[1]	auto[1]	164	1		T280	4		T281	5		T282	2
all_values[1]	auto[0]	auto[1]	318937	1		T1	1		T2	2		T3	1
all_values[1]	auto[1]	auto[1]	140	1		T280	3		T281	5		T282	1
all_values[2]	auto[0]	auto[0]	1570	1		T1	1		T2	2		T3	1
all_values[2]	auto[0]	auto[1]	44	1		T280	1		T281	2		T343	2
all_values[2]	auto[1]	auto[0]	317415	1		T6	3284		T7	9152		T28	891
all_values[2]	auto[1]	auto[1]	48	1		T280	4		T281	2		T282	1
all_values[3]	auto[0]	auto[0]	1573	1		T1	1		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	48	1		T280	1		T281	1		T282	1
all_values[3]	auto[1]	auto[0]	93034	1		T6	1642		T7	223		T28	340
all_values[3]	auto[1]	auto[1]	224422	1		T6	1642		T7	8929		T28	551
all_values[4]	auto[0]	auto[0]	1111	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	512	1		T2	1		T18	1		T4	1
all_values[4]	auto[1]	auto[0]	206065	1		T6	1642		T7	7375		T28	340
all_values[4]	auto[1]	auto[1]	111389	1		T6	1642		T7	1777		T28	551
all_values[5]	auto[0]	auto[0]	1467	1		T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	137	1		T2	1		T39	1		T40	1
all_values[5]	auto[1]	auto[0]	317406	1		T6	3284		T7	9152		T28	891
all_values[5]	auto[1]	auto[1]	67	1		T280	1		T281	4		T282	1