Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	1	15	93.75

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	1	15	93.75	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	242005	1		T1	1		T2	1875		T3	8
auto[FlashEraseBank]	273548	1		T1	9		T2	1551		T3	5

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	264221	1		T2	1446		T3	12		T6	1642
auto[FlashOpProgram]	232208	1		T1	10		T2	1980		T3	1
auto[FlashOpErase]	15124	1		T18	30		T4	9		T5	6
auto[FlashOpInvalid]	4000	1		T20	200		T45	200		T150	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	264221	1		T2	1446		T3	12		T6	1642
op[FlashOpProgram]	232208	1		T1	10		T2	1980		T3	1
op[FlashOpErase]	15124	1		T18	30		T4	9		T5	6
read_erase_read	527	1		T4	2		T30	16		T138	8
read_prog_read	837	1		T2	11		T3	1		T27	1

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	379049	1		T1	1		T2	2944		T3	1
auto[FlashPartInfo]	133263	1		T1	9		T2	466		T3	11
auto[FlashPartInfo1]	717	1		T2	4		T62	3		T39	2
auto[FlashPartInfo2]	2524	1		T2	12		T3	1		T43	5

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for op_part_cross

Uncovered bins

part_cp	op_cp	COUNT	AT LEAST	NUMBER
[auto[FlashPartInfo1]]	[auto[FlashOpInvalid]]	0	1	1

Covered bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	196302	1		T2	1103		T3	1		T6	1642
auto[FlashPartData]	auto[FlashOpProgram]	175130	1		T1	1		T2	1841		T57	13
auto[FlashPartData]	auto[FlashOpErase]	3701	1		T18	30		T5	6		T20	99
auto[FlashPartData]	auto[FlashOpInvalid]	3916	1		T20	198		T45	198		T150	196
auto[FlashPartInfo]	auto[FlashOpRead]	65776	1		T2	333		T3	10		T12	1
auto[FlashPartInfo]	auto[FlashOpProgram]	56022	1		T1	9		T2	133		T3	1
auto[FlashPartInfo]	auto[FlashOpErase]	11393	1		T4	9		T20	1		T102	181
auto[FlashPartInfo]	auto[FlashOpInvalid]	72	1		T20	2		T45	2		T150	4
auto[FlashPartInfo1]	auto[FlashOpRead]	553	1		T2	4		T62	3		T39	2
auto[FlashPartInfo1]	auto[FlashOpProgram]	163	1		T38	32		T65	32		T233	1
auto[FlashPartInfo1]	auto[FlashOpErase]	1	1		T361	1		-	-		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1590	1		T2	6		T3	1		T43	4
auto[FlashPartInfo2]	auto[FlashOpProgram]	893	1		T2	6		T43	1		T62	7
auto[FlashPartInfo2]	auto[FlashOpErase]	29	1		T30	1		T140	1		T232	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	12	1		T144	2		T362	2		T363	2