Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29853	1		T18	4		T4	4		T5	8
auto[1]	51	1		T86	3		T213	1		T149	9
auto[2]	82	1		T18	12		T138	11		T149	4
auto[3]	240	1		T3	1		T27	1		T30	22

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7566	1		T3	1		T18	4		T4	1
evic_idx[1]	7559	1		T18	4		T4	1		T5	2
evic_idx[2]	7547	1		T18	4		T4	1		T5	2
evic_idx[3]	7554	1		T18	4		T27	1		T4	1

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	29237	1		T20	400		T102	368		T45	400
evic_op[2]	323	1		T3	1		T27	1		T4	4

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7243	1		T20	100		T102	92		T45	100
evic_idx[0]	evic_op[1]	auto[1]	12	1		T149	4		T143	1		T421	4
evic_idx[0]	evic_op[1]	auto[2]	11	1		T138	2		T149	1		T422	3
evic_idx[0]	evic_op[1]	auto[3]	52	1		T30	7		T143	3		T421	1
evic_idx[0]	evic_op[2]	auto[0]	64	1		T4	1		T238	1		T423	3
evic_idx[0]	evic_op[2]	auto[1]	4	1		T86	1		T309	1		T424	1
evic_idx[0]	evic_op[2]	auto[2]	1	1		T425	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[3]	12	1		T3	1		T134	1		T426	1
evic_idx[1]	evic_op[1]	auto[0]	7242	1		T20	100		T102	92		T45	100
evic_idx[1]	evic_op[1]	auto[1]	8	1		T149	2		T143	1		T421	3
evic_idx[1]	evic_op[1]	auto[2]	11	1		T138	3		T149	2		T422	1
evic_idx[1]	evic_op[1]	auto[3]	48	1		T30	5		T143	3		T427	2
evic_idx[1]	evic_op[2]	auto[0]	62	1		T4	1		T238	1		T423	3
evic_idx[1]	evic_op[2]	auto[1]	4	1		T86	1		T309	1		T428	1
evic_idx[1]	evic_op[2]	auto[2]	1	1		T42	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[3]	16	1		T29	1		T55	1		T429	1
evic_idx[2]	evic_op[1]	auto[0]	7243	1		T20	100		T102	92		T45	100
evic_idx[2]	evic_op[1]	auto[1]	9	1		T149	1		T143	1		T421	4
evic_idx[2]	evic_op[1]	auto[2]	8	1		T138	2		T422	2		T430	2
evic_idx[2]	evic_op[1]	auto[3]	43	1		T30	5		T143	3		T427	1
evic_idx[2]	evic_op[2]	auto[0]	59	1		T4	1		T22	1		T238	1
evic_idx[2]	evic_op[2]	auto[1]	2	1		T213	1		T431	1		-	-
evic_idx[2]	evic_op[2]	auto[2]	5	1		T42	1		T432	1		T433	1
evic_idx[2]	evic_op[2]	auto[3]	12	1		T434	1		T435	1		T436	1
evic_idx[3]	evic_op[1]	auto[0]	7244	1		T20	100		T102	92		T45	100
evic_idx[3]	evic_op[1]	auto[1]	7	1		T149	2		T143	1		T421	1
evic_idx[3]	evic_op[1]	auto[2]	11	1		T138	4		T149	1		T422	1
evic_idx[3]	evic_op[1]	auto[3]	45	1		T30	5		T143	5		T427	2
evic_idx[3]	evic_op[2]	auto[0]	62	1		T4	1		T21	1		T168	1
evic_idx[3]	evic_op[2]	auto[1]	5	1		T86	1		T437	1		T438	1
evic_idx[3]	evic_op[2]	auto[2]	2	1		T439	1		T254	1		-	-
evic_idx[3]	evic_op[2]	auto[3]	12	1		T27	1		T223	1		T440	1