Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	22935	1		T303	1740		T348	2397		T349	1398
rd_lvl[2]	43655	1		T303	1198		T350	1351		T311	1483
rd_lvl[3]	12572	1		T7	1365		T303	566		T351	1066
rd_lvl[4]	21282	1		T7	6323		T303	519		T351	1330
rd_lvl[5]	8311	1		T7	1050		T303	273		T352	2543
rd_lvl[6]	14924	1		T303	57		T352	1225		T351	89
rd_lvl[7]	7018	1		T303	225		T353	396		T354	97
rd_lvl[8]	13249	1		T239	2920		T303	231		T353	270
rd_lvl[9]	6802	1		T239	324		T355	426		T303	334
rd_lvl[10]	14805	1		T355	1362		T303	115		T353	155
rd_lvl[11]	6724	1		T37	555		T303	162		T356	122
rd_lvl[12]	7987	1		T6	311		T37	1324		T356	1
rd_lvl[13]	5307	1		T6	1331		T34	297		T37	1
rd_lvl[14]	11988	1		T34	206		T303	101		T357	1151
rd_lvl[15]	2852	1		T28	226		T34	1		T176	51