Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	319077	1		T1	1		T2	2		T3	1
all_pins[1]	319077	1		T1	1		T2	2		T3	1
all_pins[2]	319077	1		T1	1		T2	2		T3	1
all_pins[3]	319077	1		T1	1		T2	2		T3	1
all_pins[4]	319077	1		T1	1		T2	2		T3	1
all_pins[5]	319077	1		T1	1		T2	2		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1594839	1		T1	6		T2	12		T3	6
values[0x1]	319623	1		T6	3284		T7	10556		T28	1541
transitions[0x0=>0x1]	295617	1		T6	3284		T7	8988		T28	891
transitions[0x1=>0x0]	295599	1		T6	3284		T7	8988		T28	891

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	318913	1		T1	1		T2	2		T3	1
all_pins[0]	values[0x1]	164	1		T280	4		T281	5		T282	2
all_pins[0]	transitions[0x0=>0x1]	71	1		T280	3		T281	1		T282	1
all_pins[0]	transitions[0x1=>0x0]	47	1		T280	2		T281	1		T345	2
all_pins[1]	values[0x0]	318937	1		T1	1		T2	2		T3	1
all_pins[1]	values[0x1]	140	1		T280	3		T281	5		T282	1
all_pins[1]	transitions[0x0=>0x1]	122	1		T280	2		T281	4		T282	1
all_pins[1]	transitions[0x1=>0x0]	1623	1		T28	325		T176	24		T364	1225
all_pins[2]	values[0x0]	317436	1		T1	1		T2	2		T3	1
all_pins[2]	values[0x1]	1641	1		T28	325		T176	24		T364	1225
all_pins[2]	transitions[0x0=>0x1]	30	1		T280	3		T281	2		T282	1
all_pins[2]	transitions[0x1=>0x0]	200583	1		T6	1642		T7	8738		T28	226
all_pins[3]	values[0x0]	116883	1		T1	1		T2	2		T3	1
all_pins[3]	values[0x1]	202194	1		T6	1642		T7	8738		T28	551
all_pins[3]	transitions[0x0=>0x1]	179972	1		T6	1642		T7	7170		T28	226
all_pins[3]	transitions[0x1=>0x0]	93195	1		T6	1642		T7	250		T28	340
all_pins[4]	values[0x0]	203660	1		T1	1		T2	2		T3	1
all_pins[4]	values[0x1]	115417	1		T6	1642		T7	1818		T28	665
all_pins[4]	transitions[0x0=>0x1]	115399	1		T6	1642		T7	1818		T28	665
all_pins[4]	transitions[0x1=>0x0]	49	1		T281	1		T282	1		T344	1
all_pins[5]	values[0x0]	319010	1		T1	1		T2	2		T3	1
all_pins[5]	values[0x1]	67	1		T280	1		T281	4		T282	1
all_pins[5]	transitions[0x0=>0x1]	23	1		T281	1		T345	3		T346	1
all_pins[5]	transitions[0x1=>0x0]	102	1		T280	3		T281	1		T282	1