| T1081 |
/workspace/coverage/default/39.flash_ctrl_connect.1481548746 |
|
|
Jul 01 07:00:28 PM PDT 24 |
Jul 01 07:00:45 PM PDT 24 |
98169700 ps |
| T1082 |
/workspace/coverage/default/29.flash_ctrl_otp_reset.4234674797 |
|
|
Jul 01 06:59:19 PM PDT 24 |
Jul 01 07:01:35 PM PDT 24 |
37341900 ps |
| T1083 |
/workspace/coverage/default/8.flash_ctrl_error_mp.2499924847 |
|
|
Jul 01 06:54:48 PM PDT 24 |
Jul 01 07:33:34 PM PDT 24 |
22834447600 ps |
| T1084 |
/workspace/coverage/default/18.flash_ctrl_invalid_op.2531971308 |
|
|
Jul 01 06:57:30 PM PDT 24 |
Jul 01 06:58:43 PM PDT 24 |
8723864600 ps |
| T1085 |
/workspace/coverage/default/9.flash_ctrl_invalid_op.138586955 |
|
|
Jul 01 06:55:12 PM PDT 24 |
Jul 01 06:56:47 PM PDT 24 |
2368820000 ps |
| T1086 |
/workspace/coverage/default/5.flash_ctrl_rand_ops.1256080697 |
|
|
Jul 01 06:53:52 PM PDT 24 |
Jul 01 06:58:05 PM PDT 24 |
105281100 ps |
| T1087 |
/workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.683503612 |
|
|
Jul 01 06:57:37 PM PDT 24 |
Jul 01 06:57:52 PM PDT 24 |
15839400 ps |
| T1088 |
/workspace/coverage/default/4.flash_ctrl_fetch_code.1770712593 |
|
|
Jul 01 06:53:37 PM PDT 24 |
Jul 01 06:54:04 PM PDT 24 |
3403044700 ps |
| T1089 |
/workspace/coverage/default/5.flash_ctrl_prog_reset.969826191 |
|
|
Jul 01 06:54:01 PM PDT 24 |
Jul 01 06:54:16 PM PDT 24 |
29926800 ps |
| T1090 |
/workspace/coverage/default/1.flash_ctrl_erase_suspend.3453801068 |
|
|
Jul 01 06:52:27 PM PDT 24 |
Jul 01 06:57:32 PM PDT 24 |
1482299700 ps |
| T1091 |
/workspace/coverage/default/11.flash_ctrl_smoke.1044154063 |
|
|
Jul 01 06:55:37 PM PDT 24 |
Jul 01 06:57:46 PM PDT 24 |
60757100 ps |
| T1092 |
/workspace/coverage/default/10.flash_ctrl_wo.32757862 |
|
|
Jul 01 06:55:41 PM PDT 24 |
Jul 01 06:59:08 PM PDT 24 |
2899525400 ps |
| T1093 |
/workspace/coverage/default/5.flash_ctrl_mp_regions.3318355405 |
|
|
Jul 01 06:53:52 PM PDT 24 |
Jul 01 07:02:46 PM PDT 24 |
16353232000 ps |
| T1094 |
/workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.4126957632 |
|
|
Jul 01 06:56:34 PM PDT 24 |
Jul 01 06:59:13 PM PDT 24 |
23437912600 ps |
| T1095 |
/workspace/coverage/default/25.flash_ctrl_intr_rd.3524790369 |
|
|
Jul 01 06:58:32 PM PDT 24 |
Jul 01 07:00:46 PM PDT 24 |
670425800 ps |
| T1096 |
/workspace/coverage/default/31.flash_ctrl_disable.3102059030 |
|
|
Jul 01 06:59:26 PM PDT 24 |
Jul 01 06:59:50 PM PDT 24 |
20958000 ps |
| T175 |
/workspace/coverage/default/1.flash_ctrl_mid_op_rst.887866997 |
|
|
Jul 01 06:52:29 PM PDT 24 |
Jul 01 06:53:46 PM PDT 24 |
3043305500 ps |
| T1097 |
/workspace/coverage/default/2.flash_ctrl_hw_rma_reset.972836940 |
|
|
Jul 01 06:52:47 PM PDT 24 |
Jul 01 07:08:58 PM PDT 24 |
40126877900 ps |
| T1098 |
/workspace/coverage/default/8.flash_ctrl_intr_wr.509044602 |
|
|
Jul 01 06:54:48 PM PDT 24 |
Jul 01 06:55:52 PM PDT 24 |
6988737200 ps |
| T1099 |
/workspace/coverage/default/5.flash_ctrl_intr_rd.932178487 |
|
|
Jul 01 06:53:51 PM PDT 24 |
Jul 01 06:56:19 PM PDT 24 |
1068262900 ps |
| T1100 |
/workspace/coverage/default/59.flash_ctrl_connect.2981356341 |
|
|
Jul 01 07:01:11 PM PDT 24 |
Jul 01 07:01:28 PM PDT 24 |
30502500 ps |
| T1101 |
/workspace/coverage/default/44.flash_ctrl_alert_test.939020140 |
|
|
Jul 01 07:00:40 PM PDT 24 |
Jul 01 07:00:56 PM PDT 24 |
35666600 ps |
| T1102 |
/workspace/coverage/default/2.flash_ctrl_read_word_sweep_derr.1442531869 |
|
|
Jul 01 06:52:55 PM PDT 24 |
Jul 01 06:53:24 PM PDT 24 |
332239400 ps |
| T1103 |
/workspace/coverage/default/6.flash_ctrl_lcmgr_intg.1027782851 |
|
|
Jul 01 06:54:23 PM PDT 24 |
Jul 01 06:54:37 PM PDT 24 |
25132400 ps |
| T1104 |
/workspace/coverage/default/7.flash_ctrl_disable.3878018378 |
|
|
Jul 01 06:54:41 PM PDT 24 |
Jul 01 06:55:04 PM PDT 24 |
69170700 ps |
| T1105 |
/workspace/coverage/default/4.flash_ctrl_error_prog_win.3105510254 |
|
|
Jul 01 06:53:29 PM PDT 24 |
Jul 01 07:08:09 PM PDT 24 |
1759066200 ps |
| T1106 |
/workspace/coverage/default/1.flash_ctrl_disable.2977755971 |
|
|
Jul 01 06:52:47 PM PDT 24 |
Jul 01 06:53:11 PM PDT 24 |
18722900 ps |
| T1107 |
/workspace/coverage/default/17.flash_ctrl_wo.2045787919 |
|
|
Jul 01 06:57:20 PM PDT 24 |
Jul 01 06:59:43 PM PDT 24 |
1892022200 ps |
| T1108 |
/workspace/coverage/default/48.flash_ctrl_connect.2230851485 |
|
|
Jul 01 07:00:49 PM PDT 24 |
Jul 01 07:01:07 PM PDT 24 |
14408500 ps |
| T1109 |
/workspace/coverage/default/43.flash_ctrl_otp_reset.3148861380 |
|
|
Jul 01 07:00:38 PM PDT 24 |
Jul 01 07:02:52 PM PDT 24 |
152259300 ps |
| T115 |
/workspace/coverage/default/0.flash_ctrl_sec_cm.3178031923 |
|
|
Jul 01 06:52:21 PM PDT 24 |
Jul 01 08:16:09 PM PDT 24 |
9473109200 ps |
| T1110 |
/workspace/coverage/default/42.flash_ctrl_connect.1884064021 |
|
|
Jul 01 07:00:37 PM PDT 24 |
Jul 01 07:00:55 PM PDT 24 |
16689300 ps |
| T1111 |
/workspace/coverage/default/36.flash_ctrl_connect.142305953 |
|
|
Jul 01 06:59:51 PM PDT 24 |
Jul 01 07:00:05 PM PDT 24 |
31724000 ps |
| T1112 |
/workspace/coverage/default/29.flash_ctrl_alert_test.3885325479 |
|
|
Jul 01 06:59:28 PM PDT 24 |
Jul 01 06:59:43 PM PDT 24 |
52382300 ps |
| T1113 |
/workspace/coverage/default/26.flash_ctrl_rw_evict_all_en.49896193 |
|
|
Jul 01 06:58:41 PM PDT 24 |
Jul 01 06:59:10 PM PDT 24 |
51470000 ps |
| T1114 |
/workspace/coverage/default/9.flash_ctrl_prog_reset.475476036 |
|
|
Jul 01 06:55:24 PM PDT 24 |
Jul 01 06:55:38 PM PDT 24 |
82520800 ps |
| T187 |
/workspace/coverage/default/3.flash_ctrl_prog_reset.3380300748 |
|
|
Jul 01 06:53:06 PM PDT 24 |
Jul 01 06:53:23 PM PDT 24 |
26118400 ps |
| T1115 |
/workspace/coverage/default/57.flash_ctrl_connect.27942427 |
|
|
Jul 01 07:01:04 PM PDT 24 |
Jul 01 07:01:20 PM PDT 24 |
193475200 ps |
| T1116 |
/workspace/coverage/default/30.flash_ctrl_rw_evict_all_en.3328840170 |
|
|
Jul 01 06:59:27 PM PDT 24 |
Jul 01 07:00:00 PM PDT 24 |
28471700 ps |
| T1117 |
/workspace/coverage/default/7.flash_ctrl_ro_serr.3241670956 |
|
|
Jul 01 06:54:33 PM PDT 24 |
Jul 01 06:57:15 PM PDT 24 |
668151800 ps |
| T1118 |
/workspace/coverage/default/55.flash_ctrl_otp_reset.1744037257 |
|
|
Jul 01 07:01:03 PM PDT 24 |
Jul 01 07:03:23 PM PDT 24 |
155790600 ps |
| T1119 |
/workspace/coverage/default/3.flash_ctrl_invalid_op.889516431 |
|
|
Jul 01 06:53:05 PM PDT 24 |
Jul 01 06:54:14 PM PDT 24 |
3393980900 ps |
| T1120 |
/workspace/coverage/default/12.flash_ctrl_intr_rd.2382252892 |
|
|
Jul 01 06:55:59 PM PDT 24 |
Jul 01 06:58:35 PM PDT 24 |
3142719500 ps |
| T1121 |
/workspace/coverage/default/35.flash_ctrl_disable.810616361 |
|
|
Jul 01 06:59:41 PM PDT 24 |
Jul 01 07:00:04 PM PDT 24 |
55177900 ps |
| T1122 |
/workspace/coverage/default/0.flash_ctrl_host_dir_rd.190673223 |
|
|
Jul 01 06:52:22 PM PDT 24 |
Jul 01 06:54:21 PM PDT 24 |
237187700 ps |
| T108 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.3286355963 |
|
|
Jul 01 04:57:23 PM PDT 24 |
Jul 01 04:57:48 PM PDT 24 |
118291100 ps |
| T280 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.2706947324 |
|
|
Jul 01 04:57:20 PM PDT 24 |
Jul 01 04:57:38 PM PDT 24 |
16682100 ps |
| T281 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.2949030356 |
|
|
Jul 01 04:57:23 PM PDT 24 |
Jul 01 04:57:41 PM PDT 24 |
48143100 ps |
| T282 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.1108372226 |
|
|
Jul 01 04:57:00 PM PDT 24 |
Jul 01 04:57:25 PM PDT 24 |
24511200 ps |
| T343 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.2343031331 |
|
|
Jul 01 04:57:36 PM PDT 24 |
Jul 01 04:57:58 PM PDT 24 |
80817700 ps |
| T1123 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1294981779 |
|
|
Jul 01 04:57:06 PM PDT 24 |
Jul 01 04:57:31 PM PDT 24 |
24522900 ps |
| T66 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.738065307 |
|
|
Jul 01 04:57:09 PM PDT 24 |
Jul 01 04:57:38 PM PDT 24 |
63602900 ps |
| T344 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.1071785732 |
|
|
Jul 01 04:57:26 PM PDT 24 |
Jul 01 04:57:45 PM PDT 24 |
29781900 ps |
| T67 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.4081544195 |
|
|
Jul 01 04:57:01 PM PDT 24 |
Jul 01 05:03:42 PM PDT 24 |
537283000 ps |
| T345 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.915484246 |
|
|
Jul 01 04:57:22 PM PDT 24 |
Jul 01 04:57:40 PM PDT 24 |
17857100 ps |
| T347 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.2184764172 |
|
|
Jul 01 04:57:06 PM PDT 24 |
Jul 01 04:57:30 PM PDT 24 |
25184200 ps |
| T68 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.1806490936 |
|
|
Jul 01 04:57:05 PM PDT 24 |
Jul 01 04:57:30 PM PDT 24 |
132604200 ps |
| T109 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.4087501381 |
|
|
Jul 01 04:57:11 PM PDT 24 |
Jul 01 05:12:24 PM PDT 24 |
509547800 ps |
| T1124 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.4290572932 |
|
|
Jul 01 04:57:27 PM PDT 24 |
Jul 01 04:57:48 PM PDT 24 |
20068700 ps |
| T276 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.460309116 |
|
|
Jul 01 04:57:02 PM PDT 24 |
Jul 01 04:58:01 PM PDT 24 |
2192483300 ps |
| T227 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.4123186682 |
|
|
Jul 01 04:57:06 PM PDT 24 |
Jul 01 05:05:02 PM PDT 24 |
947790000 ps |
| T1125 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1285441882 |
|
|
Jul 01 04:57:09 PM PDT 24 |
Jul 01 04:57:36 PM PDT 24 |
36206400 ps |
| T1126 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.71290785 |
|
|
Jul 01 04:57:22 PM PDT 24 |
Jul 01 04:57:40 PM PDT 24 |
70808500 ps |
| T346 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.560112736 |
|
|
Jul 01 04:57:00 PM PDT 24 |
Jul 01 04:57:25 PM PDT 24 |
27072700 ps |
| T262 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2449145023 |
|
|
Jul 01 04:57:17 PM PDT 24 |
Jul 01 04:57:54 PM PDT 24 |
1786328000 ps |
| T1127 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.636871045 |
|
|
Jul 01 04:57:00 PM PDT 24 |
Jul 01 04:57:24 PM PDT 24 |
46315200 ps |
| T1128 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.504569885 |
|
|
Jul 01 04:57:15 PM PDT 24 |
Jul 01 04:57:38 PM PDT 24 |
22153900 ps |
| T325 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.2794123093 |
|
|
Jul 01 04:57:05 PM PDT 24 |
Jul 01 04:58:08 PM PDT 24 |
6397219600 ps |
| T263 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2700039983 |
|
|
Jul 01 04:57:20 PM PDT 24 |
Jul 01 04:57:39 PM PDT 24 |
139748200 ps |
| T326 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.388174181 |
|
|
Jul 01 04:57:04 PM PDT 24 |
Jul 01 04:57:32 PM PDT 24 |
195585400 ps |
| T264 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1050643860 |
|
|
Jul 01 04:57:16 PM PDT 24 |
Jul 01 04:57:41 PM PDT 24 |
111946000 ps |
| T226 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.343231127 |
|
|
Jul 01 04:57:14 PM PDT 24 |
Jul 01 04:57:41 PM PDT 24 |
41695600 ps |
| T1129 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.633737462 |
|
|
Jul 01 04:56:58 PM PDT 24 |
Jul 01 04:57:21 PM PDT 24 |
25580100 ps |
| T1130 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1809150743 |
|
|
Jul 01 04:57:14 PM PDT 24 |
Jul 01 04:57:35 PM PDT 24 |
14173900 ps |
| T265 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.1500224221 |
|
|
Jul 01 04:57:12 PM PDT 24 |
Jul 01 04:57:38 PM PDT 24 |
204374300 ps |
| T240 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3384884549 |
|
|
Jul 01 04:57:21 PM PDT 24 |
Jul 01 04:57:44 PM PDT 24 |
56884400 ps |
| T1131 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.1787795661 |
|
|
Jul 01 04:57:15 PM PDT 24 |
Jul 01 04:57:36 PM PDT 24 |
91748500 ps |
| T266 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1777342176 |
|
|
Jul 01 04:57:04 PM PDT 24 |
Jul 01 04:57:50 PM PDT 24 |
302210000 ps |
| T442 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.3502809046 |
|
|
Jul 01 04:56:58 PM PDT 24 |
Jul 01 04:58:04 PM PDT 24 |
881833800 ps |
| T1132 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2377211345 |
|
|
Jul 01 04:57:00 PM PDT 24 |
Jul 01 04:57:26 PM PDT 24 |
24584900 ps |
| T241 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.1442046048 |
|
|
Jul 01 04:57:04 PM PDT 24 |
Jul 01 04:57:30 PM PDT 24 |
31795900 ps |
| T1133 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2610191866 |
|
|
Jul 01 04:57:11 PM PDT 24 |
Jul 01 04:57:36 PM PDT 24 |
43621100 ps |
| T1134 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.802160522 |
|
|
Jul 01 04:57:08 PM PDT 24 |
Jul 01 04:57:33 PM PDT 24 |
14662200 ps |
| T1135 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.3052346369 |
|
|
Jul 01 04:57:17 PM PDT 24 |
Jul 01 04:57:39 PM PDT 24 |
39857300 ps |
| T242 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.806114586 |
|
|
Jul 01 04:57:06 PM PDT 24 |
Jul 01 04:57:35 PM PDT 24 |
99160100 ps |
| T1136 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.1715672421 |
|
|
Jul 01 04:57:03 PM PDT 24 |
Jul 01 04:57:27 PM PDT 24 |
53677900 ps |
| T267 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.694634114 |
|
|
Jul 01 04:57:14 PM PDT 24 |
Jul 01 04:57:40 PM PDT 24 |
171938000 ps |
| T268 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.310705646 |
|
|
Jul 01 04:57:11 PM PDT 24 |
Jul 01 04:57:42 PM PDT 24 |
169761400 ps |
| T1137 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.1818411434 |
|
|
Jul 01 04:57:17 PM PDT 24 |
Jul 01 04:57:39 PM PDT 24 |
36878600 ps |
| T1138 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.2771504367 |
|
|
Jul 01 04:57:07 PM PDT 24 |
Jul 01 04:57:38 PM PDT 24 |
113189400 ps |
| T327 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.2145713975 |
|
|
Jul 01 04:57:24 PM PDT 24 |
Jul 01 04:57:48 PM PDT 24 |
267565200 ps |
| T1139 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3555484914 |
|
|
Jul 01 04:57:36 PM PDT 24 |
Jul 01 04:57:57 PM PDT 24 |
57052400 ps |
| T1140 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.3471776286 |
|
|
Jul 01 04:57:02 PM PDT 24 |
Jul 01 04:57:28 PM PDT 24 |
24088400 ps |
| T246 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.11772543 |
|
|
Jul 01 04:56:59 PM PDT 24 |
Jul 01 04:57:22 PM PDT 24 |
53742900 ps |
| T374 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1914033439 |
|
|
Jul 01 04:57:00 PM PDT 24 |
Jul 01 04:58:26 PM PDT 24 |
2476365100 ps |
| T247 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.14346371 |
|
|
Jul 01 04:57:15 PM PDT 24 |
Jul 01 04:57:36 PM PDT 24 |
61434500 ps |
| T328 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.994286271 |
|
|
Jul 01 04:57:12 PM PDT 24 |
Jul 01 04:57:37 PM PDT 24 |
421690400 ps |
| T1141 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2241146604 |
|
|
Jul 01 04:57:24 PM PDT 24 |
Jul 01 04:57:45 PM PDT 24 |
19851500 ps |
| T1142 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.862882118 |
|
|
Jul 01 04:57:25 PM PDT 24 |
Jul 01 04:57:44 PM PDT 24 |
14924000 ps |
| T243 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.3394877498 |
|
|
Jul 01 04:57:12 PM PDT 24 |
Jul 01 04:57:38 PM PDT 24 |
43259700 ps |
| T1143 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.2424129931 |
|
|
Jul 01 04:57:18 PM PDT 24 |
Jul 01 04:57:37 PM PDT 24 |
172163100 ps |
| T1144 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3180293421 |
|
|
Jul 01 04:57:04 PM PDT 24 |
Jul 01 04:57:31 PM PDT 24 |
13460200 ps |
| T244 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.1140094252 |
|
|
Jul 01 04:56:56 PM PDT 24 |
Jul 01 05:03:28 PM PDT 24 |
811685400 ps |
| T375 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1017485315 |
|
|
Jul 01 04:57:07 PM PDT 24 |
Jul 01 04:57:33 PM PDT 24 |
33307100 ps |
| T245 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.3205351886 |
|
|
Jul 01 04:57:14 PM PDT 24 |
Jul 01 04:57:40 PM PDT 24 |
558985700 ps |
| T283 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1076324718 |
|
|
Jul 01 04:57:31 PM PDT 24 |
Jul 01 04:57:55 PM PDT 24 |
442188100 ps |
| T1145 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.3973663458 |
|
|
Jul 01 04:57:01 PM PDT 24 |
Jul 01 04:57:28 PM PDT 24 |
19290900 ps |
| T1146 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.1504902365 |
|
|
Jul 01 04:57:09 PM PDT 24 |
Jul 01 04:57:36 PM PDT 24 |
23748600 ps |
| T1147 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.2161655912 |
|
|
Jul 01 04:57:32 PM PDT 24 |
Jul 01 04:57:53 PM PDT 24 |
92058400 ps |
| T1148 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.1364927971 |
|
|
Jul 01 04:57:14 PM PDT 24 |
Jul 01 04:57:35 PM PDT 24 |
40417500 ps |
| T329 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.809612023 |
|
|
Jul 01 04:57:01 PM PDT 24 |
Jul 01 04:57:57 PM PDT 24 |
407932000 ps |
| T330 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1785317622 |
|
|
Jul 01 04:57:33 PM PDT 24 |
Jul 01 04:57:59 PM PDT 24 |
88603300 ps |
| T1149 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.4271747971 |
|
|
Jul 01 04:57:13 PM PDT 24 |
Jul 01 04:57:41 PM PDT 24 |
171488100 ps |
| T279 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.4122141852 |
|
|
Jul 01 04:57:13 PM PDT 24 |
Jul 01 04:57:41 PM PDT 24 |
51971900 ps |
| T277 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.558945094 |
|
|
Jul 01 04:57:18 PM PDT 24 |
Jul 01 04:57:42 PM PDT 24 |
269708600 ps |
| T1150 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.1707818354 |
|
|
Jul 01 04:57:05 PM PDT 24 |
Jul 01 04:57:32 PM PDT 24 |
34829100 ps |
| T292 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.4067267657 |
|
|
Jul 01 04:57:12 PM PDT 24 |
Jul 01 04:57:38 PM PDT 24 |
588202800 ps |
| T1151 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2444025008 |
|
|
Jul 01 04:57:04 PM PDT 24 |
Jul 01 04:57:35 PM PDT 24 |
679410000 ps |
| T1152 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.1461985660 |
|
|
Jul 01 04:57:05 PM PDT 24 |
Jul 01 04:57:29 PM PDT 24 |
16297100 ps |
| T1153 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.298006343 |
|
|
Jul 01 04:57:08 PM PDT 24 |
Jul 01 04:58:11 PM PDT 24 |
1814322600 ps |
| T331 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.2463472751 |
|
|
Jul 01 04:57:05 PM PDT 24 |
Jul 01 04:58:01 PM PDT 24 |
3752382500 ps |
| T1154 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.282210555 |
|
|
Jul 01 04:57:01 PM PDT 24 |
Jul 01 04:57:49 PM PDT 24 |
20732000 ps |
| T1155 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2995683003 |
|
|
Jul 01 04:57:11 PM PDT 24 |
Jul 01 04:58:02 PM PDT 24 |
1370347600 ps |
| T1156 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.3170477259 |
|
|
Jul 01 04:57:21 PM PDT 24 |
Jul 01 04:57:44 PM PDT 24 |
46751900 ps |
| T1157 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.2466679412 |
|
|
Jul 01 04:57:07 PM PDT 24 |
Jul 01 04:57:39 PM PDT 24 |
1845302700 ps |
| T1158 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.933090050 |
|
|
Jul 01 04:57:50 PM PDT 24 |
Jul 01 04:58:14 PM PDT 24 |
28933200 ps |
| T1159 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.224898796 |
|
|
Jul 01 04:57:21 PM PDT 24 |
Jul 01 04:57:47 PM PDT 24 |
161484200 ps |
| T1160 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.464739786 |
|
|
Jul 01 04:57:26 PM PDT 24 |
Jul 01 04:57:45 PM PDT 24 |
25532800 ps |
| T1161 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2624162483 |
|
|
Jul 01 04:57:03 PM PDT 24 |
Jul 01 04:57:27 PM PDT 24 |
14320500 ps |
| T342 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.2439824764 |
|
|
Jul 01 04:57:12 PM PDT 24 |
Jul 01 04:57:41 PM PDT 24 |
73155400 ps |
| T1162 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.853478155 |
|
|
Jul 01 04:57:23 PM PDT 24 |
Jul 01 04:57:41 PM PDT 24 |
14923200 ps |
| T366 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.458404849 |
|
|
Jul 01 04:57:09 PM PDT 24 |
Jul 01 05:12:26 PM PDT 24 |
3717318100 ps |
| T1163 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.589413731 |
|
|
Jul 01 04:57:24 PM PDT 24 |
Jul 01 04:57:43 PM PDT 24 |
29596300 ps |
| T1164 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.575032710 |
|
|
Jul 01 04:57:07 PM PDT 24 |
Jul 01 04:57:34 PM PDT 24 |
24618500 ps |
| T1165 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.2778198578 |
|
|
Jul 01 04:57:23 PM PDT 24 |
Jul 01 04:57:42 PM PDT 24 |
32758300 ps |
| T1166 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.2244742966 |
|
|
Jul 01 04:57:08 PM PDT 24 |
Jul 01 04:57:55 PM PDT 24 |
314468800 ps |
| T1167 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.758926815 |
|
|
Jul 01 04:57:03 PM PDT 24 |
Jul 01 04:57:28 PM PDT 24 |
17326900 ps |
| T1168 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1332757793 |
|
|
Jul 01 04:57:05 PM PDT 24 |
Jul 01 04:57:31 PM PDT 24 |
33870200 ps |
| T286 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.1480247234 |
|
|
Jul 01 04:57:21 PM PDT 24 |
Jul 01 05:12:32 PM PDT 24 |
731518400 ps |
| T1169 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.2168672368 |
|
|
Jul 01 04:57:23 PM PDT 24 |
Jul 01 04:58:02 PM PDT 24 |
123995100 ps |
| T1170 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.809914093 |
|
|
Jul 01 04:57:11 PM PDT 24 |
Jul 01 04:57:37 PM PDT 24 |
22400500 ps |
| T1171 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.2861874959 |
|
|
Jul 01 04:57:10 PM PDT 24 |
Jul 01 04:57:50 PM PDT 24 |
88174600 ps |
| T296 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.3034334632 |
|
|
Jul 01 04:57:10 PM PDT 24 |
Jul 01 04:57:41 PM PDT 24 |
388068400 ps |
| T1172 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.4164473074 |
|
|
Jul 01 04:57:36 PM PDT 24 |
Jul 01 04:57:58 PM PDT 24 |
141755200 ps |
| T1173 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1641973481 |
|
|
Jul 01 04:57:04 PM PDT 24 |
Jul 01 04:57:51 PM PDT 24 |
1684150000 ps |
| T1174 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.440733397 |
|
|
Jul 01 04:57:17 PM PDT 24 |
Jul 01 04:57:37 PM PDT 24 |
107980200 ps |
| T285 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.1457674552 |
|
|
Jul 01 04:57:08 PM PDT 24 |
Jul 01 04:57:40 PM PDT 24 |
50985200 ps |
| T1175 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.1330099065 |
|
|
Jul 01 04:57:10 PM PDT 24 |
Jul 01 04:57:38 PM PDT 24 |
66802900 ps |
| T290 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.604203960 |
|
|
Jul 01 04:57:11 PM PDT 24 |
Jul 01 04:57:37 PM PDT 24 |
79904800 ps |
| T1176 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2961369636 |
|
|
Jul 01 04:57:24 PM PDT 24 |
Jul 01 04:57:43 PM PDT 24 |
43500400 ps |
| T1177 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3377267266 |
|
|
Jul 01 04:57:22 PM PDT 24 |
Jul 01 04:57:42 PM PDT 24 |
26964700 ps |
| T1178 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1804384386 |
|
|
Jul 01 04:57:31 PM PDT 24 |
Jul 01 04:57:53 PM PDT 24 |
23921200 ps |
| T248 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3581529248 |
|
|
Jul 01 04:57:00 PM PDT 24 |
Jul 01 04:57:25 PM PDT 24 |
278317400 ps |
| T1179 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3156832643 |
|
|
Jul 01 04:57:17 PM PDT 24 |
Jul 01 04:57:39 PM PDT 24 |
17451700 ps |
| T368 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.3817866759 |
|
|
Jul 01 04:57:09 PM PDT 24 |
Jul 01 05:12:39 PM PDT 24 |
897202500 ps |
| T1180 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1988069456 |
|
|
Jul 01 04:57:19 PM PDT 24 |
Jul 01 04:57:59 PM PDT 24 |
66339900 ps |
| T1181 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3886807372 |
|
|
Jul 01 04:57:18 PM PDT 24 |
Jul 01 04:57:41 PM PDT 24 |
258366500 ps |
| T1182 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.3180984906 |
|
|
Jul 01 04:57:27 PM PDT 24 |
Jul 01 04:57:48 PM PDT 24 |
86759100 ps |
| T1183 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.2208781196 |
|
|
Jul 01 04:56:58 PM PDT 24 |
Jul 01 04:57:25 PM PDT 24 |
188676700 ps |
| T369 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1595089614 |
|
|
Jul 01 04:56:58 PM PDT 24 |
Jul 01 05:03:33 PM PDT 24 |
867461800 ps |
| T1184 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.3151651343 |
|
|
Jul 01 04:57:30 PM PDT 24 |
Jul 01 04:57:50 PM PDT 24 |
56002100 ps |
| T1185 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.4294195133 |
|
|
Jul 01 04:57:26 PM PDT 24 |
Jul 01 04:57:45 PM PDT 24 |
50578400 ps |
| T1186 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.1200413455 |
|
|
Jul 01 04:57:09 PM PDT 24 |
Jul 01 04:57:40 PM PDT 24 |
122998300 ps |
| T1187 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3394338758 |
|
|
Jul 01 04:57:25 PM PDT 24 |
Jul 01 04:57:44 PM PDT 24 |
30764400 ps |
| T291 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.958120304 |
|
|
Jul 01 04:57:09 PM PDT 24 |
Jul 01 04:57:37 PM PDT 24 |
38503600 ps |
| T1188 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.2754032443 |
|
|
Jul 01 04:57:19 PM PDT 24 |
Jul 01 04:57:38 PM PDT 24 |
18090300 ps |
| T288 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2209217103 |
|
|
Jul 01 04:57:05 PM PDT 24 |
Jul 01 04:57:33 PM PDT 24 |
250546400 ps |
| T1189 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1738749435 |
|
|
Jul 01 04:57:07 PM PDT 24 |
Jul 01 05:12:29 PM PDT 24 |
3055964500 ps |
| T1190 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.3136515397 |
|
|
Jul 01 04:57:07 PM PDT 24 |
Jul 01 04:57:32 PM PDT 24 |
40985300 ps |
| T1191 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2418577015 |
|
|
Jul 01 04:57:25 PM PDT 24 |
Jul 01 04:57:45 PM PDT 24 |
44690000 ps |
| T1192 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.2463285707 |
|
|
Jul 01 04:57:10 PM PDT 24 |
Jul 01 04:57:34 PM PDT 24 |
28912300 ps |
| T1193 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.1217708027 |
|
|
Jul 01 04:57:13 PM PDT 24 |
Jul 01 04:57:37 PM PDT 24 |
26732400 ps |
| T1194 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.4032470678 |
|
|
Jul 01 04:57:07 PM PDT 24 |
Jul 01 04:57:36 PM PDT 24 |
677554400 ps |
| T293 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3655304858 |
|
|
Jul 01 04:57:04 PM PDT 24 |
Jul 01 05:12:17 PM PDT 24 |
705201500 ps |
| T1195 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.89014105 |
|
|
Jul 01 04:57:01 PM PDT 24 |
Jul 01 04:57:43 PM PDT 24 |
41326300 ps |
| T370 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.4015600822 |
|
|
Jul 01 04:57:07 PM PDT 24 |
Jul 01 05:04:57 PM PDT 24 |
354127200 ps |
| T1196 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.3161771982 |
|
|
Jul 01 04:57:02 PM PDT 24 |
Jul 01 04:57:31 PM PDT 24 |
50827200 ps |
| T1197 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.3356938928 |
|
|
Jul 01 04:57:39 PM PDT 24 |
Jul 01 04:58:01 PM PDT 24 |
65433900 ps |
| T367 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2697961407 |
|
|
Jul 01 04:57:29 PM PDT 24 |
Jul 01 05:04:02 PM PDT 24 |
2236699600 ps |
| T1198 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.957891122 |
|
|
Jul 01 04:57:09 PM PDT 24 |
Jul 01 04:57:34 PM PDT 24 |
17122200 ps |
| T1199 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.3369060528 |
|
|
Jul 01 04:57:07 PM PDT 24 |
Jul 01 04:57:37 PM PDT 24 |
328767600 ps |
| T1200 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.932217875 |
|
|
Jul 01 04:57:06 PM PDT 24 |
Jul 01 04:57:31 PM PDT 24 |
17596500 ps |
| T332 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.3563151604 |
|
|
Jul 01 04:57:18 PM PDT 24 |
Jul 01 04:57:55 PM PDT 24 |
449044700 ps |
| T1201 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.544116038 |
|
|
Jul 01 04:57:13 PM PDT 24 |
Jul 01 04:57:35 PM PDT 24 |
51231600 ps |
| T1202 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.2668201294 |
|
|
Jul 01 04:57:47 PM PDT 24 |
Jul 01 04:58:10 PM PDT 24 |
30934700 ps |
| T1203 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.2634775461 |
|
|
Jul 01 04:57:07 PM PDT 24 |
Jul 01 04:57:32 PM PDT 24 |
14828300 ps |
| T249 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.1872474900 |
|
|
Jul 01 04:56:57 PM PDT 24 |
Jul 01 04:57:20 PM PDT 24 |
144767900 ps |
| T1204 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.4042953967 |
|
|
Jul 01 04:57:06 PM PDT 24 |
Jul 01 04:57:33 PM PDT 24 |
89381600 ps |
| T1205 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.3588397285 |
|
|
Jul 01 04:57:09 PM PDT 24 |
Jul 01 04:57:33 PM PDT 24 |
13710300 ps |
| T1206 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2107240870 |
|
|
Jul 01 04:57:04 PM PDT 24 |
Jul 01 04:57:29 PM PDT 24 |
15071600 ps |
| T1207 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.2628500230 |
|
|
Jul 01 04:57:41 PM PDT 24 |
Jul 01 04:58:03 PM PDT 24 |
189956300 ps |
| T1208 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2650991834 |
|
|
Jul 01 04:57:14 PM PDT 24 |
Jul 01 04:57:39 PM PDT 24 |
85936300 ps |
| T371 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.140660171 |
|
|
Jul 01 04:57:12 PM PDT 24 |
Jul 01 05:05:07 PM PDT 24 |
3036786400 ps |
| T1209 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2796003474 |
|
|
Jul 01 04:57:10 PM PDT 24 |
Jul 01 04:57:36 PM PDT 24 |
24091800 ps |
| T1210 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2754745608 |
|
|
Jul 01 04:57:30 PM PDT 24 |
Jul 01 04:57:49 PM PDT 24 |
13820700 ps |
| T1211 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.872079443 |
|
|
Jul 01 04:57:14 PM PDT 24 |
Jul 01 04:57:38 PM PDT 24 |
13663700 ps |
| T1212 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.121162949 |
|
|
Jul 01 04:56:57 PM PDT 24 |
Jul 01 04:57:52 PM PDT 24 |
25771200 ps |
| T1213 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.3248456745 |
|
|
Jul 01 04:57:12 PM PDT 24 |
Jul 01 04:57:35 PM PDT 24 |
272346600 ps |
| T1214 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.1270526881 |
|
|
Jul 01 04:57:27 PM PDT 24 |
Jul 01 04:57:47 PM PDT 24 |
55226000 ps |
| T278 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.1192110742 |
|
|
Jul 01 04:57:01 PM PDT 24 |
Jul 01 04:57:27 PM PDT 24 |
53207400 ps |
| T1215 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.286011444 |
|
|
Jul 01 04:57:24 PM PDT 24 |
Jul 01 04:57:43 PM PDT 24 |
18631400 ps |
| T333 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.2621218525 |
|
|
Jul 01 04:57:12 PM PDT 24 |
Jul 01 04:57:41 PM PDT 24 |
206151200 ps |
| T297 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.1027866784 |
|
|
Jul 01 04:57:14 PM PDT 24 |
Jul 01 05:12:27 PM PDT 24 |
333228500 ps |
| T1216 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1524202900 |
|
|
Jul 01 04:57:27 PM PDT 24 |
Jul 01 04:57:53 PM PDT 24 |
83404000 ps |
| T1217 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.1606861642 |
|
|
Jul 01 04:57:12 PM PDT 24 |
Jul 01 04:57:38 PM PDT 24 |
373110700 ps |
| T1218 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.3683547872 |
|
|
Jul 01 04:57:23 PM PDT 24 |
Jul 01 04:57:42 PM PDT 24 |
361174900 ps |
| T1219 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.2460950887 |
|
|
Jul 01 04:57:22 PM PDT 24 |
Jul 01 04:57:40 PM PDT 24 |
70935100 ps |
| T1220 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1488411484 |
|
|
Jul 01 04:57:09 PM PDT 24 |
Jul 01 04:57:36 PM PDT 24 |
15222500 ps |
| T1221 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.413792241 |
|
|
Jul 01 04:57:21 PM PDT 24 |
Jul 01 04:57:44 PM PDT 24 |
83008600 ps |
| T1222 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.3078407410 |
|
|
Jul 01 04:57:22 PM PDT 24 |
Jul 01 04:57:40 PM PDT 24 |
16721900 ps |
| T1223 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.2602520254 |
|
|
Jul 01 04:57:10 PM PDT 24 |
Jul 01 04:57:37 PM PDT 24 |
197110900 ps |
| T1224 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.203895723 |
|
|
Jul 01 04:57:06 PM PDT 24 |
Jul 01 04:57:34 PM PDT 24 |
49347600 ps |
| T1225 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.4123803303 |
|
|
Jul 01 04:57:09 PM PDT 24 |
Jul 01 04:57:35 PM PDT 24 |
84172800 ps |
| T295 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.724821410 |
|
|
Jul 01 04:57:18 PM PDT 24 |
Jul 01 05:12:27 PM PDT 24 |
4143600700 ps |
| T287 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.1125818755 |
|
|
Jul 01 04:57:07 PM PDT 24 |
Jul 01 04:57:36 PM PDT 24 |
73411800 ps |
| T334 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2881558807 |
|
|
Jul 01 04:57:06 PM PDT 24 |
Jul 01 04:57:59 PM PDT 24 |
4325417100 ps |
| T1226 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.1796563911 |
|
|
Jul 01 04:57:07 PM PDT 24 |
Jul 01 05:05:02 PM PDT 24 |
460683500 ps |
| T1227 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.2244527555 |
|
|
Jul 01 04:57:31 PM PDT 24 |
Jul 01 04:57:52 PM PDT 24 |
20811900 ps |
| T250 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2828375461 |
|
|
Jul 01 04:57:02 PM PDT 24 |
Jul 01 04:57:26 PM PDT 24 |
14903400 ps |
| T335 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.2240780956 |
|
|
Jul 01 04:57:31 PM PDT 24 |
Jul 01 04:57:58 PM PDT 24 |
279615100 ps |
| T1228 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.445524709 |
|
|
Jul 01 04:57:04 PM PDT 24 |
Jul 01 04:57:31 PM PDT 24 |
66889500 ps |
| T1229 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.2309871740 |
|
|
Jul 01 04:57:27 PM PDT 24 |
Jul 01 04:57:49 PM PDT 24 |
102280500 ps |
| T1230 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.2811833172 |
|
|
Jul 01 04:56:54 PM PDT 24 |
Jul 01 04:57:14 PM PDT 24 |
20853900 ps |
| T1231 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.2115884051 |
|
|
Jul 01 04:57:05 PM PDT 24 |
Jul 01 04:57:33 PM PDT 24 |
39190300 ps |
| T284 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.486845162 |
|
|
Jul 01 04:57:08 PM PDT 24 |
Jul 01 04:57:34 PM PDT 24 |
37574300 ps |
| T1232 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.557601704 |
|
|
Jul 01 04:57:04 PM PDT 24 |
Jul 01 04:57:28 PM PDT 24 |
14030100 ps |
| T1233 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3138276475 |
|
|
Jul 01 04:57:34 PM PDT 24 |
Jul 01 05:05:23 PM PDT 24 |
453435000 ps |
| T294 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.654947717 |
|
|
Jul 01 04:57:19 PM PDT 24 |
Jul 01 04:57:43 PM PDT 24 |
554369800 ps |
| T1234 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1727746426 |
|
|
Jul 01 04:56:58 PM PDT 24 |
Jul 01 04:57:48 PM PDT 24 |
339171100 ps |
| T289 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2956718202 |
|
|
Jul 01 04:57:32 PM PDT 24 |
Jul 01 04:57:57 PM PDT 24 |
145994400 ps |
| T1235 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.2542456833 |
|
|
Jul 01 04:57:23 PM PDT 24 |
Jul 01 04:57:41 PM PDT 24 |
40400500 ps |
| T1236 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.115462673 |
|
|
Jul 01 04:57:34 PM PDT 24 |
Jul 01 04:57:57 PM PDT 24 |
66983200 ps |
| T1237 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1846390350 |
|
|
Jul 01 04:57:06 PM PDT 24 |
Jul 01 04:57:33 PM PDT 24 |
107635500 ps |
| T1238 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.2772877617 |
|
|
Jul 01 04:57:28 PM PDT 24 |
Jul 01 04:57:51 PM PDT 24 |
242432000 ps |
| T1239 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2491168742 |
|
|
Jul 01 04:57:18 PM PDT 24 |
Jul 01 04:57:37 PM PDT 24 |
18193100 ps |
| T1240 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.3448296986 |
|
|
Jul 01 04:57:21 PM PDT 24 |
Jul 01 04:57:40 PM PDT 24 |
81718800 ps |
| T372 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3527374179 |
|
|
Jul 01 04:57:13 PM PDT 24 |
Jul 01 05:10:03 PM PDT 24 |
3251608700 ps |
| T1241 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.880926046 |
|
|
Jul 01 04:57:03 PM PDT 24 |
Jul 01 04:57:31 PM PDT 24 |
274878800 ps |
| T365 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3076828057 |
|
|
Jul 01 04:57:04 PM PDT 24 |
Jul 01 04:57:31 PM PDT 24 |
112436300 ps |
| T1242 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.1017772883 |
|
|
Jul 01 04:57:22 PM PDT 24 |
Jul 01 04:57:40 PM PDT 24 |
40781800 ps |
| T298 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2714496303 |
|
|
Jul 01 04:57:27 PM PDT 24 |
Jul 01 04:57:53 PM PDT 24 |
212382600 ps |
| T1243 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.1942240716 |
|
|
Jul 01 04:57:00 PM PDT 24 |
Jul 01 04:58:03 PM PDT 24 |
834560100 ps |
| T1244 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.2222767055 |
|
|
Jul 01 04:57:28 PM PDT 24 |
Jul 01 04:57:48 PM PDT 24 |
85512300 ps |
| T1245 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.2173085315 |
|
|
Jul 01 04:57:04 PM PDT 24 |
Jul 01 04:57:31 PM PDT 24 |
43451800 ps |
| T1246 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3430281811 |
|
|
Jul 01 04:57:08 PM PDT 24 |
Jul 01 04:57:34 PM PDT 24 |
23653600 ps |
| T1247 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.4138737321 |
|
|
Jul 01 04:57:08 PM PDT 24 |
Jul 01 04:57:38 PM PDT 24 |
302411700 ps |
| T1248 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1206147552 |
|
|
Jul 01 04:57:20 PM PDT 24 |
Jul 01 04:57:39 PM PDT 24 |
15856100 ps |
| T1249 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3226010783 |
|
|
Jul 01 04:57:06 PM PDT 24 |
Jul 01 04:57:36 PM PDT 24 |
349673600 ps |
| T1250 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.1177390132 |
|
|
Jul 01 04:57:24 PM PDT 24 |
Jul 01 04:57:48 PM PDT 24 |
119647800 ps |
| T1251 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.3952445988 |
|
|
Jul 01 04:57:07 PM PDT 24 |
Jul 01 04:57:34 PM PDT 24 |
25570700 ps |