Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	329579	1		T1	1		T2	1		T3	2
all_values[1]	329579	1		T1	1		T2	1		T3	2
all_values[2]	329579	1		T1	1		T2	1		T3	2
all_values[3]	329579	1		T1	1		T2	1		T3	2
all_values[4]	329579	1		T1	1		T2	1		T3	2
all_values[5]	329579	1		T1	1		T2	1		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	665469	1		T1	6		T2	6		T3	12
auto[1]	1312005	1		T31	24116		T32	20352		T28	4672

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	966792	1		T1	4		T2	4		T3	7
auto[1]	1010682	1		T1	2		T2	2		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	329417	1		T1	1		T2	1		T3	2
all_values[0]	auto[1]	auto[1]	162	1		T267	5		T269	2		T327	3
all_values[1]	auto[0]	auto[1]	329402	1		T1	1		T2	1		T3	2
all_values[1]	auto[1]	auto[1]	177	1		T267	7		T268	2		T269	7
all_values[2]	auto[0]	auto[0]	1587	1		T1	1		T2	1		T3	2
all_values[2]	auto[0]	auto[1]	46	1		T267	2		T268	2		T327	1
all_values[2]	auto[1]	auto[0]	327887	1		T31	6029		T32	5088		T28	1168
all_values[2]	auto[1]	auto[1]	59	1		T267	1		T269	2		T327	1
all_values[3]	auto[0]	auto[0]	1609	1		T1	1		T2	1		T3	2
all_values[3]	auto[0]	auto[1]	58	1		T267	1		T268	1		T269	1
all_values[3]	auto[1]	auto[0]	78808	1		T31	1004		T32	1696		T28	584
all_values[3]	auto[1]	auto[1]	249104	1		T31	5025		T32	3392		T28	584
all_values[4]	auto[0]	auto[0]	1138	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	532	1		T3	1		T9	1		T5	1
all_values[4]	auto[1]	auto[0]	226370	1		T31	5023		T32	3392		T28	584
all_values[4]	auto[1]	auto[1]	101539	1		T31	1006		T32	1696		T28	584
all_values[5]	auto[0]	auto[0]	1541	1		T1	1		T2	1		T3	2
all_values[5]	auto[0]	auto[1]	139	1		T5	1		T33	1		T34	1
all_values[5]	auto[1]	auto[0]	327852	1		T31	6029		T32	5088		T28	1168
all_values[5]	auto[1]	auto[1]	47	1		T327	2		T328	3		T333	1