Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	247168	1		T1	1265		T2	7		T3	247
auto[FlashEraseBank]	279790	1		T2	6		T14	2		T9	1

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	259336	1		T1	621		T2	12		T3	10
auto[FlashOpProgram]	248256	1		T1	322		T2	1		T3	224
auto[FlashOpErase]	15366	1		T1	322		T3	13		T9	1
auto[FlashOpInvalid]	4000	1		T139	200		T141	200		T143	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	259336	1		T1	621		T2	12		T3	10
op[FlashOpProgram]	248256	1		T1	322		T2	1		T3	224
op[FlashOpErase]	15366	1		T1	322		T3	13		T9	1
read_erase_read	543	1		T3	1		T26	4		T21	2
read_prog_read	900	1		T2	1		T14	2		T5	5

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	385540	1		T2	6		T14	5		T9	2
auto[FlashPartInfo]	137797	1		T1	1265		T2	4		T3	247
auto[FlashPartInfo1]	882	1		T5	4		T20	1		T31	15
auto[FlashPartInfo2]	2739	1		T2	3		T5	17		T117	3

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	186911	1		T2	5		T14	3		T9	1
auto[FlashPartData]	auto[FlashOpProgram]	191163	1		T2	1		T14	2		T5	2069
auto[FlashPartData]	auto[FlashOpErase]	3550	1		T9	1		T17	1		T26	29
auto[FlashPartData]	auto[FlashOpInvalid]	3916	1		T139	192		T141	196		T143	192
auto[FlashPartInfo]	auto[FlashOpRead]	69923	1		T1	621		T2	4		T3	10
auto[FlashPartInfo]	auto[FlashOpProgram]	56010	1		T1	322		T3	224		T14	1
auto[FlashPartInfo]	auto[FlashOpErase]	11794	1		T1	322		T3	13		T42	75
auto[FlashPartInfo]	auto[FlashOpInvalid]	70	1		T139	6		T141	4		T143	6
auto[FlashPartInfo1]	auto[FlashOpRead]	713	1		T5	4		T20	1		T31	15
auto[FlashPartInfo1]	auto[FlashOpProgram]	163	1		T139	1		T143	1		T123	32
auto[FlashPartInfo1]	auto[FlashOpErase]	2	1		T139	1		T143	1		-	-
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T139	2		T143	2		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1789	1		T2	3		T5	8		T20	9
auto[FlashPartInfo2]	auto[FlashOpProgram]	920	1		T5	9		T117	3		T68	1
auto[FlashPartInfo2]	auto[FlashOpErase]	20	1		T151	1		T121	1		T152	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	10	1		T388	4		T389	2		T390	2