Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30212	1		T1	632		T14	1		T17	4
auto[1]	57	1		T203	1		T222	1		T280	8
auto[2]	95	1		T19	3		T58	1		T248	1
auto[3]	197	1		T14	1		T54	1		T259	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7648	1		T1	158		T17	1		T42	37
evic_idx[1]	7644	1		T1	158		T17	1		T19	1
evic_idx[2]	7635	1		T1	158		T14	1		T17	1
evic_idx[3]	7634	1		T1	158		T14	1		T17	1

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	29645	1		T1	632		T17	4		T42	148
evic_op[2]	332	1		T14	2		T19	3		T21	16

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7344	1		T1	158		T17	1		T42	37
evic_idx[0]	evic_op[1]	auto[1]	11	1		T280	1		T391	4		T392	1
evic_idx[0]	evic_op[1]	auto[2]	16	1		T248	1		T216	4		T280	3
evic_idx[0]	evic_op[1]	auto[3]	48	1		T248	1		T391	1		T393	9
evic_idx[0]	evic_op[2]	auto[0]	68	1		T21	4		T54	1		T68	1
evic_idx[0]	evic_op[2]	auto[1]	2	1		T394	1		T395	1		-	-
evic_idx[0]	evic_op[2]	auto[2]	3	1		T396	1		T397	1		T398	1
evic_idx[0]	evic_op[2]	auto[3]	10	1		T54	1		T399	1		T400	1
evic_idx[1]	evic_op[1]	auto[0]	7344	1		T1	158		T17	1		T42	37
evic_idx[1]	evic_op[1]	auto[1]	10	1		T280	2		T391	3		T401	1
evic_idx[1]	evic_op[1]	auto[2]	15	1		T216	4		T280	2		T402	4
evic_idx[1]	evic_op[1]	auto[3]	43	1		T248	1		T393	10		T392	1
evic_idx[1]	evic_op[2]	auto[0]	68	1		T21	4		T68	1		T403	1
evic_idx[1]	evic_op[2]	auto[1]	6	1		T203	1		T404	1		T405	1
evic_idx[1]	evic_op[2]	auto[2]	4	1		T19	1		T137	1		T406	1
evic_idx[1]	evic_op[2]	auto[3]	8	1		T149	1		T407	1		T399	1
evic_idx[2]	evic_op[1]	auto[0]	7345	1		T1	158		T17	1		T42	37
evic_idx[2]	evic_op[1]	auto[1]	10	1		T280	3		T391	3		T401	1
evic_idx[2]	evic_op[1]	auto[2]	15	1		T216	3		T280	2		T392	2
evic_idx[2]	evic_op[1]	auto[3]	39	1		T248	1		T393	9		T408	1
evic_idx[2]	evic_op[2]	auto[0]	68	1		T21	4		T68	1		T409	1
evic_idx[2]	evic_op[2]	auto[1]	3	1		T77	1		T410	1		T395	1
evic_idx[2]	evic_op[2]	auto[2]	1	1		T137	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[3]	8	1		T14	1		T205	1		T399	1
evic_idx[3]	evic_op[1]	auto[0]	7342	1		T1	158		T17	1		T42	37
evic_idx[3]	evic_op[1]	auto[1]	10	1		T280	2		T391	2		T401	1
evic_idx[3]	evic_op[1]	auto[2]	16	1		T216	3		T280	2		T408	1
evic_idx[3]	evic_op[1]	auto[3]	37	1		T248	1		T393	10		T392	1
evic_idx[3]	evic_op[2]	auto[0]	69	1		T14	1		T21	4		T54	1
evic_idx[3]	evic_op[2]	auto[1]	5	1		T222	1		T77	1		T411	1
evic_idx[3]	evic_op[2]	auto[2]	5	1		T19	2		T58	1		T222	1
evic_idx[3]	evic_op[2]	auto[3]	4	1		T259	1		T399	1		T412	1