Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	28831	1		T221	1602		T334	2379		T335	2141
rd_lvl[2]	37912	1		T221	864		T84	1068		T334	2350
rd_lvl[3]	16487	1		T31	2942		T221	361		T336	674
rd_lvl[4]	22854	1		T31	2079		T317	1283		T223	244
rd_lvl[5]	25238	1		T317	419		T231	2345		T223	48
rd_lvl[6]	16061	1		T31	2		T231	1318		T337	2664
rd_lvl[7]	9766	1		T32	338		T317	73		T338	131
rd_lvl[8]	18131	1		T32	1645		T338	53		T221	28
rd_lvl[9]	11149	1		T32	1405		T338	5		T221	44
rd_lvl[10]	14410	1		T31	1		T28	382		T338	3
rd_lvl[11]	3023	1		T28	147		T221	111		T339	1
rd_lvl[12]	5648	1		T317	73		T30	4		T339	64
rd_lvl[13]	1881	1		T31	1		T28	55		T340	558
rd_lvl[14]	4905	1		T221	65		T29	194		T340	1126
rd_lvl[15]	2536	1		T29	31		T341	209		T342	391