Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	329579	1		T1	1		T2	1		T3	2
all_pins[1]	329579	1		T1	1		T2	1		T3	2
all_pins[2]	329579	1		T1	1		T2	1		T3	2
all_pins[3]	329579	1		T1	1		T2	1		T3	2
all_pins[4]	329579	1		T1	1		T2	1		T3	2
all_pins[5]	329579	1		T1	1		T2	1		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1651371	1		T1	6		T2	6		T3	12
values[0x1]	326103	1		T31	6515		T32	6201		T28	1168
transitions[0x0=>0x1]	298450	1		T31	6029		T32	5084		T28	1168
transitions[0x1=>0x0]	298432	1		T31	6029		T32	5084		T28	1168

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	329417	1		T1	1		T2	1		T3	2
all_pins[0]	values[0x1]	162	1		T267	5		T269	2		T327	3
all_pins[0]	transitions[0x0=>0x1]	72	1		T327	3		T329	3		T328	4
all_pins[0]	transitions[0x1=>0x0]	87	1		T267	2		T268	2		T269	5
all_pins[1]	values[0x0]	329402	1		T1	1		T2	1		T3	2
all_pins[1]	values[0x1]	177	1		T267	7		T268	2		T269	7
all_pins[1]	transitions[0x0=>0x1]	144	1		T267	6		T268	2		T269	5
all_pins[1]	transitions[0x1=>0x0]	162	1		T29	54		T341	72		T344	10
all_pins[2]	values[0x0]	329384	1		T1	1		T2	1		T3	2
all_pins[2]	values[0x1]	195	1		T29	54		T341	72		T344	10
all_pins[2]	transitions[0x0=>0x1]	45	1		T267	1		T269	2		T329	2
all_pins[2]	transitions[0x1=>0x0]	219050	1		T31	5025		T32	3388		T28	584
all_pins[3]	values[0x0]	110379	1		T1	1		T2	1		T3	2
all_pins[3]	values[0x1]	219200	1		T31	5025		T32	3388		T28	584
all_pins[3]	transitions[0x0=>0x1]	191866	1		T31	4539		T32	2271		T28	584
all_pins[3]	transitions[0x1=>0x0]	78988	1		T31	1004		T32	1696		T28	584
all_pins[4]	values[0x0]	223257	1		T1	1		T2	1		T3	2
all_pins[4]	values[0x1]	106322	1		T31	1490		T32	2813		T28	584
all_pins[4]	transitions[0x0=>0x1]	106305	1		T31	1490		T32	2813		T28	584
all_pins[4]	transitions[0x1=>0x0]	30	1		T327	2		T328	2		T333	1
all_pins[5]	values[0x0]	329532	1		T1	1		T2	1		T3	2
all_pins[5]	values[0x1]	47	1		T327	2		T328	3		T333	1
all_pins[5]	transitions[0x0=>0x1]	18	1		T327	1		T328	1		T345	1
all_pins[5]	transitions[0x1=>0x0]	115	1		T267	4		T269	2		T327	1