| T1074 |
/workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.4290061133 |
|
|
Jul 02 08:48:34 AM PDT 24 |
Jul 02 08:49:56 AM PDT 24 |
10019292400 ps |
| T255 |
/workspace/coverage/default/2.flash_ctrl_rw_derr.518721745 |
|
|
Jul 02 08:48:50 AM PDT 24 |
Jul 02 08:59:56 AM PDT 24 |
7300710000 ps |
| T1075 |
/workspace/coverage/default/0.flash_ctrl_error_mp.449267902 |
|
|
Jul 02 08:47:49 AM PDT 24 |
Jul 02 09:30:59 AM PDT 24 |
16651364400 ps |
| T1076 |
/workspace/coverage/default/15.flash_ctrl_prog_reset.1480339141 |
|
|
Jul 02 08:53:33 AM PDT 24 |
Jul 02 08:53:47 AM PDT 24 |
74964200 ps |
| T1077 |
/workspace/coverage/default/19.flash_ctrl_hw_read_seed_err.2474462475 |
|
|
Jul 02 08:54:30 AM PDT 24 |
Jul 02 08:54:44 AM PDT 24 |
46835000 ps |
| T1078 |
/workspace/coverage/default/36.flash_ctrl_hw_sec_otp.2838006914 |
|
|
Jul 02 08:56:13 AM PDT 24 |
Jul 02 08:58:19 AM PDT 24 |
2564357000 ps |
| T1079 |
/workspace/coverage/default/30.flash_ctrl_smoke.3640022979 |
|
|
Jul 02 08:55:38 AM PDT 24 |
Jul 02 08:57:43 AM PDT 24 |
43001400 ps |
| T1080 |
/workspace/coverage/default/13.flash_ctrl_rw.2645079836 |
|
|
Jul 02 08:52:57 AM PDT 24 |
Jul 02 09:04:17 AM PDT 24 |
3871473000 ps |
| T1081 |
/workspace/coverage/default/17.flash_ctrl_re_evict.472653549 |
|
|
Jul 02 08:53:57 AM PDT 24 |
Jul 02 08:54:30 AM PDT 24 |
190268500 ps |
| T1082 |
/workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.1877405675 |
|
|
Jul 02 08:54:17 AM PDT 24 |
Jul 02 08:56:37 AM PDT 24 |
10012502400 ps |
| T1083 |
/workspace/coverage/default/36.flash_ctrl_disable.1035829905 |
|
|
Jul 02 08:56:12 AM PDT 24 |
Jul 02 08:56:35 AM PDT 24 |
40117100 ps |
| T1084 |
/workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.740834988 |
|
|
Jul 02 08:56:14 AM PDT 24 |
Jul 02 09:00:24 AM PDT 24 |
35367481900 ps |
| T62 |
/workspace/coverage/default/2.flash_ctrl_phy_ack_consistency.2957748858 |
|
|
Jul 02 08:49:01 AM PDT 24 |
Jul 02 08:49:16 AM PDT 24 |
32948900 ps |
| T1085 |
/workspace/coverage/default/3.flash_ctrl_invalid_op.2926143928 |
|
|
Jul 02 08:49:18 AM PDT 24 |
Jul 02 08:50:22 AM PDT 24 |
2049357100 ps |
| T1086 |
/workspace/coverage/default/32.flash_ctrl_rw_evict.2535869965 |
|
|
Jul 02 08:55:54 AM PDT 24 |
Jul 02 08:56:26 AM PDT 24 |
27872500 ps |
| T1087 |
/workspace/coverage/default/35.flash_ctrl_smoke.55838860 |
|
|
Jul 02 08:56:07 AM PDT 24 |
Jul 02 08:58:57 AM PDT 24 |
86954600 ps |
| T1088 |
/workspace/coverage/default/3.flash_ctrl_phy_arb.3910836230 |
|
|
Jul 02 08:49:08 AM PDT 24 |
Jul 02 08:56:23 AM PDT 24 |
3660332600 ps |
| T1089 |
/workspace/coverage/default/11.flash_ctrl_prog_reset.2120297320 |
|
|
Jul 02 08:52:23 AM PDT 24 |
Jul 02 08:55:18 AM PDT 24 |
2586804300 ps |
| T1090 |
/workspace/coverage/default/35.flash_ctrl_alert_test.3038243894 |
|
|
Jul 02 08:56:12 AM PDT 24 |
Jul 02 08:56:28 AM PDT 24 |
22787000 ps |
| T1091 |
/workspace/coverage/default/5.flash_ctrl_ro.3014986729 |
|
|
Jul 02 08:50:22 AM PDT 24 |
Jul 02 08:52:16 AM PDT 24 |
666253400 ps |
| T1092 |
/workspace/coverage/default/8.flash_ctrl_rand_ops.3423456773 |
|
|
Jul 02 08:51:16 AM PDT 24 |
Jul 02 09:10:42 AM PDT 24 |
9892596500 ps |
| T1093 |
/workspace/coverage/default/12.flash_ctrl_intr_rd.2381068009 |
|
|
Jul 02 08:52:44 AM PDT 24 |
Jul 02 08:55:46 AM PDT 24 |
4678931300 ps |
| T1094 |
/workspace/coverage/default/0.flash_ctrl_ro_serr.1008743787 |
|
|
Jul 02 08:47:46 AM PDT 24 |
Jul 02 08:50:28 AM PDT 24 |
633814800 ps |
| T1095 |
/workspace/coverage/default/7.flash_ctrl_connect.4071958286 |
|
|
Jul 02 08:51:07 AM PDT 24 |
Jul 02 08:51:23 AM PDT 24 |
61188400 ps |
| T1096 |
/workspace/coverage/default/6.flash_ctrl_smoke.2270496719 |
|
|
Jul 02 08:50:31 AM PDT 24 |
Jul 02 08:53:47 AM PDT 24 |
48127900 ps |
| T1097 |
/workspace/coverage/default/16.flash_ctrl_rw_evict_all_en.2326553396 |
|
|
Jul 02 08:53:43 AM PDT 24 |
Jul 02 08:54:16 AM PDT 24 |
120871700 ps |
| T1098 |
/workspace/coverage/default/29.flash_ctrl_hw_sec_otp.1586925604 |
|
|
Jul 02 08:55:32 AM PDT 24 |
Jul 02 08:57:30 AM PDT 24 |
6194087100 ps |
| T1099 |
/workspace/coverage/default/5.flash_ctrl_intr_wr_slow_flash.1423107891 |
|
|
Jul 02 08:50:32 AM PDT 24 |
Jul 02 08:53:34 AM PDT 24 |
51753145200 ps |
| T1100 |
/workspace/coverage/default/17.flash_ctrl_otp_reset.2123516244 |
|
|
Jul 02 08:53:55 AM PDT 24 |
Jul 02 08:55:47 AM PDT 24 |
76286800 ps |
| T1101 |
/workspace/coverage/default/1.flash_ctrl_oversize_error.2699022946 |
|
|
Jul 02 08:48:11 AM PDT 24 |
Jul 02 08:51:06 AM PDT 24 |
1637655400 ps |
| T1102 |
/workspace/coverage/default/6.flash_ctrl_fetch_code.2872847144 |
|
|
Jul 02 08:50:36 AM PDT 24 |
Jul 02 08:51:00 AM PDT 24 |
886740200 ps |
| T1103 |
/workspace/coverage/default/18.flash_ctrl_wo.2329010481 |
|
|
Jul 02 08:54:13 AM PDT 24 |
Jul 02 08:57:09 AM PDT 24 |
34107963000 ps |
| T1104 |
/workspace/coverage/default/12.flash_ctrl_invalid_op.2151036041 |
|
|
Jul 02 08:52:35 AM PDT 24 |
Jul 02 08:54:02 AM PDT 24 |
4016867500 ps |
| T1105 |
/workspace/coverage/default/7.flash_ctrl_intr_wr_slow_flash.2235323113 |
|
|
Jul 02 08:51:03 AM PDT 24 |
Jul 02 08:53:45 AM PDT 24 |
18698176200 ps |
| T1106 |
/workspace/coverage/default/14.flash_ctrl_hw_sec_otp.4004352502 |
|
|
Jul 02 08:53:06 AM PDT 24 |
Jul 02 08:55:33 AM PDT 24 |
2012713100 ps |
| T1107 |
/workspace/coverage/default/20.flash_ctrl_hw_sec_otp.1826073905 |
|
|
Jul 02 08:54:36 AM PDT 24 |
Jul 02 08:56:08 AM PDT 24 |
2511623300 ps |
| T1108 |
/workspace/coverage/default/32.flash_ctrl_otp_reset.2249645328 |
|
|
Jul 02 08:55:50 AM PDT 24 |
Jul 02 08:58:06 AM PDT 24 |
253305600 ps |
| T1109 |
/workspace/coverage/default/21.flash_ctrl_otp_reset.2737462432 |
|
|
Jul 02 08:54:39 AM PDT 24 |
Jul 02 08:56:52 AM PDT 24 |
133284400 ps |
| T1110 |
/workspace/coverage/default/15.flash_ctrl_sec_info_access.1804717849 |
|
|
Jul 02 08:53:32 AM PDT 24 |
Jul 02 08:54:38 AM PDT 24 |
3928647100 ps |
| T1111 |
/workspace/coverage/default/25.flash_ctrl_prog_reset.235727919 |
|
|
Jul 02 08:55:05 AM PDT 24 |
Jul 02 08:55:22 AM PDT 24 |
77026600 ps |
| T1112 |
/workspace/coverage/default/52.flash_ctrl_connect.3532428180 |
|
|
Jul 02 08:57:16 AM PDT 24 |
Jul 02 08:57:33 AM PDT 24 |
16579600 ps |
| T1113 |
/workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.4178047188 |
|
|
Jul 02 08:56:00 AM PDT 24 |
Jul 02 09:05:02 AM PDT 24 |
49917196800 ps |
| T1114 |
/workspace/coverage/default/14.flash_ctrl_rw.4183062001 |
|
|
Jul 02 08:53:15 AM PDT 24 |
Jul 02 09:02:41 AM PDT 24 |
15686848500 ps |
| T1115 |
/workspace/coverage/default/30.flash_ctrl_rw_evict_all_en.717211897 |
|
|
Jul 02 08:55:41 AM PDT 24 |
Jul 02 08:56:12 AM PDT 24 |
62693400 ps |
| T1116 |
/workspace/coverage/default/20.flash_ctrl_alert_test.2880830060 |
|
|
Jul 02 08:54:38 AM PDT 24 |
Jul 02 08:54:53 AM PDT 24 |
54677600 ps |
| T1117 |
/workspace/coverage/default/74.flash_ctrl_connect.2448781283 |
|
|
Jul 02 08:57:36 AM PDT 24 |
Jul 02 08:57:55 AM PDT 24 |
14526800 ps |
| T1118 |
/workspace/coverage/default/15.flash_ctrl_alert_test.1926947732 |
|
|
Jul 02 08:53:33 AM PDT 24 |
Jul 02 08:53:47 AM PDT 24 |
38438200 ps |
| T1119 |
/workspace/coverage/default/13.flash_ctrl_intr_rd_slow_flash.3495675455 |
|
|
Jul 02 08:52:56 AM PDT 24 |
Jul 02 08:55:20 AM PDT 24 |
5837705500 ps |
| T63 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1110600414 |
|
|
Jul 02 09:59:53 AM PDT 24 |
Jul 02 10:00:14 AM PDT 24 |
112658600 ps |
| T64 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.164451253 |
|
|
Jul 02 09:59:48 AM PDT 24 |
Jul 02 10:12:21 AM PDT 24 |
4187850500 ps |
| T65 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.2806672576 |
|
|
Jul 02 09:59:39 AM PDT 24 |
Jul 02 10:00:01 AM PDT 24 |
115262100 ps |
| T96 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2916602078 |
|
|
Jul 02 09:59:54 AM PDT 24 |
Jul 02 10:07:45 AM PDT 24 |
688374800 ps |
| T201 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.4082145360 |
|
|
Jul 02 10:00:00 AM PDT 24 |
Jul 02 10:12:51 AM PDT 24 |
1455231500 ps |
| T267 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2351719641 |
|
|
Jul 02 09:59:31 AM PDT 24 |
Jul 02 09:59:46 AM PDT 24 |
51999600 ps |
| T268 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.4149037181 |
|
|
Jul 02 10:00:02 AM PDT 24 |
Jul 02 10:00:20 AM PDT 24 |
54149800 ps |
| T1120 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2817260368 |
|
|
Jul 02 09:59:33 AM PDT 24 |
Jul 02 09:59:48 AM PDT 24 |
27754600 ps |
| T1121 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.3262803568 |
|
|
Jul 02 09:59:47 AM PDT 24 |
Jul 02 10:00:04 AM PDT 24 |
14569100 ps |
| T269 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.4051306197 |
|
|
Jul 02 09:59:50 AM PDT 24 |
Jul 02 10:00:04 AM PDT 24 |
17504300 ps |
| T256 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.54334361 |
|
|
Jul 02 09:59:28 AM PDT 24 |
Jul 02 09:59:48 AM PDT 24 |
37967900 ps |
| T257 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.985800432 |
|
|
Jul 02 09:59:42 AM PDT 24 |
Jul 02 10:00:01 AM PDT 24 |
339034000 ps |
| T327 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.3783892786 |
|
|
Jul 02 10:00:07 AM PDT 24 |
Jul 02 10:00:27 AM PDT 24 |
16332500 ps |
| T241 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.977286765 |
|
|
Jul 02 09:59:45 AM PDT 24 |
Jul 02 10:06:09 AM PDT 24 |
177402600 ps |
| T329 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.2979553719 |
|
|
Jul 02 10:00:12 AM PDT 24 |
Jul 02 10:00:31 AM PDT 24 |
15441300 ps |
| T1122 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1513599154 |
|
|
Jul 02 09:59:41 AM PDT 24 |
Jul 02 09:59:56 AM PDT 24 |
41102900 ps |
| T326 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.3249291670 |
|
|
Jul 02 09:59:34 AM PDT 24 |
Jul 02 10:00:34 AM PDT 24 |
660154000 ps |
| T199 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.4293984520 |
|
|
Jul 02 09:59:47 AM PDT 24 |
Jul 02 10:00:02 AM PDT 24 |
104146700 ps |
| T1123 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.686760394 |
|
|
Jul 02 09:59:44 AM PDT 24 |
Jul 02 10:00:01 AM PDT 24 |
15667300 ps |
| T1124 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.1238791927 |
|
|
Jul 02 09:59:48 AM PDT 24 |
Jul 02 10:00:05 AM PDT 24 |
30948400 ps |
| T236 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.4247834765 |
|
|
Jul 02 09:59:54 AM PDT 24 |
Jul 02 10:06:21 AM PDT 24 |
1372360500 ps |
| T258 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.2916678469 |
|
|
Jul 02 09:59:45 AM PDT 24 |
Jul 02 10:00:01 AM PDT 24 |
67450100 ps |
| T330 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2680573537 |
|
|
Jul 02 09:59:47 AM PDT 24 |
Jul 02 10:00:02 AM PDT 24 |
15244900 ps |
| T1125 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.2280009708 |
|
|
Jul 02 09:59:48 AM PDT 24 |
Jul 02 10:00:10 AM PDT 24 |
319241600 ps |
| T328 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.1723638506 |
|
|
Jul 02 09:59:46 AM PDT 24 |
Jul 02 10:00:00 AM PDT 24 |
17359800 ps |
| T1126 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.251284444 |
|
|
Jul 02 09:59:45 AM PDT 24 |
Jul 02 10:00:03 AM PDT 24 |
12124000 ps |
| T1127 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.707858328 |
|
|
Jul 02 09:59:42 AM PDT 24 |
Jul 02 09:59:58 AM PDT 24 |
13474700 ps |
| T333 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.3884002190 |
|
|
Jul 02 10:00:05 AM PDT 24 |
Jul 02 10:00:24 AM PDT 24 |
33263900 ps |
| T200 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.99016042 |
|
|
Jul 02 09:59:46 AM PDT 24 |
Jul 02 10:00:03 AM PDT 24 |
40804500 ps |
| T1128 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2741434222 |
|
|
Jul 02 09:59:51 AM PDT 24 |
Jul 02 10:00:10 AM PDT 24 |
97904300 ps |
| T304 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.2167899398 |
|
|
Jul 02 09:59:33 AM PDT 24 |
Jul 02 09:59:52 AM PDT 24 |
263911300 ps |
| T237 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3249325792 |
|
|
Jul 02 10:00:00 AM PDT 24 |
Jul 02 10:00:19 AM PDT 24 |
125933100 ps |
| T1129 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.4136942211 |
|
|
Jul 02 09:59:47 AM PDT 24 |
Jul 02 10:00:01 AM PDT 24 |
51193300 ps |
| T1130 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.4081148836 |
|
|
Jul 02 09:59:37 AM PDT 24 |
Jul 02 09:59:56 AM PDT 24 |
45191400 ps |
| T1131 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3249638532 |
|
|
Jul 02 09:59:42 AM PDT 24 |
Jul 02 09:59:57 AM PDT 24 |
30424800 ps |
| T1132 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.3216959384 |
|
|
Jul 02 09:59:42 AM PDT 24 |
Jul 02 10:00:22 AM PDT 24 |
651188700 ps |
| T1133 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.1803453066 |
|
|
Jul 02 09:59:54 AM PDT 24 |
Jul 02 10:00:11 AM PDT 24 |
45810100 ps |
| T305 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1590908296 |
|
|
Jul 02 09:59:37 AM PDT 24 |
Jul 02 10:00:50 AM PDT 24 |
3315420900 ps |
| T1134 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.3264344185 |
|
|
Jul 02 09:59:26 AM PDT 24 |
Jul 02 09:59:41 AM PDT 24 |
11682800 ps |
| T238 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.948501074 |
|
|
Jul 02 09:59:53 AM PDT 24 |
Jul 02 10:00:11 AM PDT 24 |
51817700 ps |
| T1135 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.1253362327 |
|
|
Jul 02 09:59:43 AM PDT 24 |
Jul 02 10:00:01 AM PDT 24 |
43097900 ps |
| T1136 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2961194187 |
|
|
Jul 02 09:59:42 AM PDT 24 |
Jul 02 10:00:01 AM PDT 24 |
121880500 ps |
| T345 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1070440907 |
|
|
Jul 02 09:59:52 AM PDT 24 |
Jul 02 10:00:10 AM PDT 24 |
19007200 ps |
| T239 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1976477853 |
|
|
Jul 02 09:59:31 AM PDT 24 |
Jul 02 09:59:51 AM PDT 24 |
61672600 ps |
| T331 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.205140742 |
|
|
Jul 02 10:00:03 AM PDT 24 |
Jul 02 10:00:22 AM PDT 24 |
26535500 ps |
| T240 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.2120908477 |
|
|
Jul 02 09:59:23 AM PDT 24 |
Jul 02 09:59:45 AM PDT 24 |
99213800 ps |
| T1137 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.1835943823 |
|
|
Jul 02 09:59:58 AM PDT 24 |
Jul 02 10:00:14 AM PDT 24 |
140536500 ps |
| T242 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2790993640 |
|
|
Jul 02 09:59:48 AM PDT 24 |
Jul 02 10:00:05 AM PDT 24 |
118530600 ps |
| T1138 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.93678929 |
|
|
Jul 02 09:59:54 AM PDT 24 |
Jul 02 10:00:10 AM PDT 24 |
19243700 ps |
| T276 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3382127308 |
|
|
Jul 02 09:59:50 AM PDT 24 |
Jul 02 10:06:15 AM PDT 24 |
832749200 ps |
| T260 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.2157286431 |
|
|
Jul 02 09:59:51 AM PDT 24 |
Jul 02 10:00:10 AM PDT 24 |
34987700 ps |
| T243 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1893187848 |
|
|
Jul 02 09:59:57 AM PDT 24 |
Jul 02 10:00:13 AM PDT 24 |
64821300 ps |
| T1139 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.3339272388 |
|
|
Jul 02 09:59:48 AM PDT 24 |
Jul 02 10:00:03 AM PDT 24 |
56626500 ps |
| T272 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.2319476355 |
|
|
Jul 02 09:59:47 AM PDT 24 |
Jul 02 10:15:11 AM PDT 24 |
9421313600 ps |
| T1140 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.110612699 |
|
|
Jul 02 09:59:42 AM PDT 24 |
Jul 02 10:00:00 AM PDT 24 |
21522200 ps |
| T1141 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.530117025 |
|
|
Jul 02 09:59:44 AM PDT 24 |
Jul 02 10:00:01 AM PDT 24 |
23741600 ps |
| T275 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.2453499737 |
|
|
Jul 02 09:59:52 AM PDT 24 |
Jul 02 10:00:13 AM PDT 24 |
62545300 ps |
| T1142 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.131544025 |
|
|
Jul 02 10:00:01 AM PDT 24 |
Jul 02 10:00:20 AM PDT 24 |
22148200 ps |
| T332 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.275036970 |
|
|
Jul 02 09:59:49 AM PDT 24 |
Jul 02 10:00:04 AM PDT 24 |
56708500 ps |
| T270 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.1495779672 |
|
|
Jul 02 09:59:47 AM PDT 24 |
Jul 02 10:00:07 AM PDT 24 |
36706000 ps |
| T1143 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.2122315738 |
|
|
Jul 02 09:59:54 AM PDT 24 |
Jul 02 10:00:11 AM PDT 24 |
40441400 ps |
| T1144 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2322945801 |
|
|
Jul 02 09:59:37 AM PDT 24 |
Jul 02 10:00:11 AM PDT 24 |
29547800 ps |
| T1145 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2725536445 |
|
|
Jul 02 09:59:59 AM PDT 24 |
Jul 02 10:00:14 AM PDT 24 |
14496200 ps |
| T1146 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1269451938 |
|
|
Jul 02 09:59:55 AM PDT 24 |
Jul 02 10:00:15 AM PDT 24 |
34177600 ps |
| T1147 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.3171000593 |
|
|
Jul 02 09:59:50 AM PDT 24 |
Jul 02 10:00:05 AM PDT 24 |
121116300 ps |
| T1148 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.522298224 |
|
|
Jul 02 09:59:32 AM PDT 24 |
Jul 02 09:59:52 AM PDT 24 |
137117200 ps |
| T1149 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.507954074 |
|
|
Jul 02 09:59:43 AM PDT 24 |
Jul 02 10:00:01 AM PDT 24 |
38393900 ps |
| T306 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2834648450 |
|
|
Jul 02 09:59:49 AM PDT 24 |
Jul 02 10:00:20 AM PDT 24 |
176868400 ps |
| T1150 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.1456717839 |
|
|
Jul 02 09:59:52 AM PDT 24 |
Jul 02 10:00:08 AM PDT 24 |
18158500 ps |
| T1151 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.2046029411 |
|
|
Jul 02 09:59:38 AM PDT 24 |
Jul 02 09:59:54 AM PDT 24 |
60978200 ps |
| T274 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.18545151 |
|
|
Jul 02 09:59:31 AM PDT 24 |
Jul 02 10:07:11 AM PDT 24 |
663575300 ps |
| T278 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3193519574 |
|
|
Jul 02 10:00:01 AM PDT 24 |
Jul 02 10:07:46 AM PDT 24 |
2723460500 ps |
| T1152 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.386546845 |
|
|
Jul 02 09:59:37 AM PDT 24 |
Jul 02 09:59:56 AM PDT 24 |
16642800 ps |
| T266 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.1047385525 |
|
|
Jul 02 09:59:38 AM PDT 24 |
Jul 02 10:00:00 AM PDT 24 |
204443200 ps |
| T307 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.4017013218 |
|
|
Jul 02 09:59:35 AM PDT 24 |
Jul 02 10:01:02 AM PDT 24 |
12819239400 ps |
| T308 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.2537965174 |
|
|
Jul 02 09:59:44 AM PDT 24 |
Jul 02 10:00:17 AM PDT 24 |
99835400 ps |
| T279 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.374813680 |
|
|
Jul 02 09:59:39 AM PDT 24 |
Jul 02 10:14:41 AM PDT 24 |
866048900 ps |
| T1153 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.901391638 |
|
|
Jul 02 09:59:56 AM PDT 24 |
Jul 02 10:00:12 AM PDT 24 |
32053100 ps |
| T1154 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1271596012 |
|
|
Jul 02 09:59:56 AM PDT 24 |
Jul 02 10:00:14 AM PDT 24 |
17367300 ps |
| T1155 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.905261367 |
|
|
Jul 02 09:59:53 AM PDT 24 |
Jul 02 10:00:17 AM PDT 24 |
661198100 ps |
| T354 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.3352384507 |
|
|
Jul 02 09:59:49 AM PDT 24 |
Jul 02 10:07:26 AM PDT 24 |
440802800 ps |
| T1156 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.3850196737 |
|
|
Jul 02 09:59:51 AM PDT 24 |
Jul 02 10:00:11 AM PDT 24 |
103018000 ps |
| T1157 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.1258043562 |
|
|
Jul 02 09:59:52 AM PDT 24 |
Jul 02 10:00:11 AM PDT 24 |
26040400 ps |
| T263 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.13727987 |
|
|
Jul 02 09:59:51 AM PDT 24 |
Jul 02 10:00:09 AM PDT 24 |
58454300 ps |
| T273 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.1759813801 |
|
|
Jul 02 09:59:41 AM PDT 24 |
Jul 02 10:00:02 AM PDT 24 |
294374600 ps |
| T352 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.3176189691 |
|
|
Jul 02 09:59:52 AM PDT 24 |
Jul 02 10:07:30 AM PDT 24 |
333634600 ps |
| T1158 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.108899437 |
|
|
Jul 02 09:59:30 AM PDT 24 |
Jul 02 10:00:11 AM PDT 24 |
30177200 ps |
| T1159 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1526691570 |
|
|
Jul 02 09:59:48 AM PDT 24 |
Jul 02 10:00:11 AM PDT 24 |
579335700 ps |
| T1160 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.3374401327 |
|
|
Jul 02 09:59:52 AM PDT 24 |
Jul 02 10:00:10 AM PDT 24 |
16769100 ps |
| T1161 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3700262774 |
|
|
Jul 02 09:59:50 AM PDT 24 |
Jul 02 10:00:10 AM PDT 24 |
668839100 ps |
| T357 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.2000472785 |
|
|
Jul 02 09:59:44 AM PDT 24 |
Jul 02 10:07:32 AM PDT 24 |
237775000 ps |
| T1162 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.79215988 |
|
|
Jul 02 09:59:56 AM PDT 24 |
Jul 02 10:00:16 AM PDT 24 |
197922900 ps |
| T1163 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.1006327346 |
|
|
Jul 02 09:59:50 AM PDT 24 |
Jul 02 10:00:05 AM PDT 24 |
12179300 ps |
| T1164 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.1454604635 |
|
|
Jul 02 10:00:00 AM PDT 24 |
Jul 02 10:00:16 AM PDT 24 |
13404500 ps |
| T1165 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.1526589697 |
|
|
Jul 02 09:59:52 AM PDT 24 |
Jul 02 10:00:08 AM PDT 24 |
59338800 ps |
| T309 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.151206538 |
|
|
Jul 02 09:59:58 AM PDT 24 |
Jul 02 10:00:16 AM PDT 24 |
136613800 ps |
| T1166 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.884977426 |
|
|
Jul 02 09:59:50 AM PDT 24 |
Jul 02 10:00:06 AM PDT 24 |
112392900 ps |
| T264 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.4239278700 |
|
|
Jul 02 09:59:52 AM PDT 24 |
Jul 02 10:00:14 AM PDT 24 |
80289300 ps |
| T265 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2282934342 |
|
|
Jul 02 09:59:37 AM PDT 24 |
Jul 02 09:59:59 AM PDT 24 |
55248100 ps |
| T1167 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.4012351213 |
|
|
Jul 02 09:59:34 AM PDT 24 |
Jul 02 09:59:50 AM PDT 24 |
64123600 ps |
| T1168 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.2157301421 |
|
|
Jul 02 09:59:49 AM PDT 24 |
Jul 02 10:00:09 AM PDT 24 |
61528800 ps |
| T1169 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.762128024 |
|
|
Jul 02 09:59:50 AM PDT 24 |
Jul 02 10:00:05 AM PDT 24 |
18323900 ps |
| T1170 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1168013854 |
|
|
Jul 02 09:59:56 AM PDT 24 |
Jul 02 10:00:15 AM PDT 24 |
15349600 ps |
| T1171 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.2572180970 |
|
|
Jul 02 10:00:00 AM PDT 24 |
Jul 02 10:00:17 AM PDT 24 |
142780600 ps |
| T271 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1926825813 |
|
|
Jul 02 09:59:49 AM PDT 24 |
Jul 02 10:00:09 AM PDT 24 |
55675300 ps |
| T1172 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1873395770 |
|
|
Jul 02 09:59:50 AM PDT 24 |
Jul 02 10:00:07 AM PDT 24 |
14095200 ps |
| T346 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3711236432 |
|
|
Jul 02 09:59:35 AM PDT 24 |
Jul 02 09:59:54 AM PDT 24 |
109999500 ps |
| T1173 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.459040604 |
|
|
Jul 02 10:00:11 AM PDT 24 |
Jul 02 10:00:30 AM PDT 24 |
20330100 ps |
| T1174 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.3206260477 |
|
|
Jul 02 09:59:48 AM PDT 24 |
Jul 02 10:00:05 AM PDT 24 |
43167800 ps |
| T1175 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.857195721 |
|
|
Jul 02 09:59:35 AM PDT 24 |
Jul 02 09:59:53 AM PDT 24 |
50399000 ps |
| T277 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.3864482444 |
|
|
Jul 02 09:59:59 AM PDT 24 |
Jul 02 10:00:22 AM PDT 24 |
150383100 ps |
| T1176 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.950192748 |
|
|
Jul 02 09:59:43 AM PDT 24 |
Jul 02 10:00:00 AM PDT 24 |
37712400 ps |
| T1177 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1029763297 |
|
|
Jul 02 09:59:59 AM PDT 24 |
Jul 02 10:00:15 AM PDT 24 |
48305800 ps |
| T1178 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1155256023 |
|
|
Jul 02 09:59:51 AM PDT 24 |
Jul 02 10:00:09 AM PDT 24 |
41735600 ps |
| T1179 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.1747492841 |
|
|
Jul 02 09:59:57 AM PDT 24 |
Jul 02 10:00:16 AM PDT 24 |
68228200 ps |
| T244 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.29251186 |
|
|
Jul 02 09:59:41 AM PDT 24 |
Jul 02 09:59:58 AM PDT 24 |
16507000 ps |
| T1180 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.300961225 |
|
|
Jul 02 09:59:59 AM PDT 24 |
Jul 02 10:00:15 AM PDT 24 |
21177800 ps |
| T353 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.2619566658 |
|
|
Jul 02 09:59:53 AM PDT 24 |
Jul 02 10:06:20 AM PDT 24 |
382122000 ps |
| T1181 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3998412842 |
|
|
Jul 02 09:59:50 AM PDT 24 |
Jul 02 10:00:05 AM PDT 24 |
20767500 ps |
| T1182 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.1634508871 |
|
|
Jul 02 09:59:52 AM PDT 24 |
Jul 02 10:00:09 AM PDT 24 |
24573300 ps |
| T310 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1192501613 |
|
|
Jul 02 10:00:01 AM PDT 24 |
Jul 02 10:00:41 AM PDT 24 |
407481600 ps |
| T1183 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.2939329582 |
|
|
Jul 02 09:59:59 AM PDT 24 |
Jul 02 10:00:17 AM PDT 24 |
21896200 ps |
| T1184 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.3213130719 |
|
|
Jul 02 09:59:41 AM PDT 24 |
Jul 02 09:59:56 AM PDT 24 |
11781800 ps |
| T1185 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.3471893866 |
|
|
Jul 02 09:59:29 AM PDT 24 |
Jul 02 09:59:49 AM PDT 24 |
54577900 ps |
| T348 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.163297176 |
|
|
Jul 02 09:59:55 AM PDT 24 |
Jul 02 10:00:17 AM PDT 24 |
278714000 ps |
| T347 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.3731645710 |
|
|
Jul 02 09:59:40 AM PDT 24 |
Jul 02 10:00:02 AM PDT 24 |
163126400 ps |
| T311 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.2289035113 |
|
|
Jul 02 09:59:54 AM PDT 24 |
Jul 02 10:00:17 AM PDT 24 |
117244200 ps |
| T1186 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.2343203979 |
|
|
Jul 02 09:59:57 AM PDT 24 |
Jul 02 10:00:13 AM PDT 24 |
99658200 ps |
| T1187 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.737096950 |
|
|
Jul 02 09:59:48 AM PDT 24 |
Jul 02 10:00:03 AM PDT 24 |
112523600 ps |
| T1188 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.4291292832 |
|
|
Jul 02 09:59:28 AM PDT 24 |
Jul 02 09:59:48 AM PDT 24 |
67399600 ps |
| T1189 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.4156287284 |
|
|
Jul 02 09:59:35 AM PDT 24 |
Jul 02 09:59:55 AM PDT 24 |
13471300 ps |
| T1190 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.2828499302 |
|
|
Jul 02 09:59:38 AM PDT 24 |
Jul 02 10:00:00 AM PDT 24 |
57522200 ps |
| T1191 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.205378668 |
|
|
Jul 02 09:59:26 AM PDT 24 |
Jul 02 10:14:23 AM PDT 24 |
1698392300 ps |
| T1192 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2191141564 |
|
|
Jul 02 09:59:39 AM PDT 24 |
Jul 02 09:59:58 AM PDT 24 |
49019900 ps |
| T350 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3643513143 |
|
|
Jul 02 09:59:52 AM PDT 24 |
Jul 02 10:14:41 AM PDT 24 |
340045300 ps |
| T1193 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.3989402525 |
|
|
Jul 02 09:59:43 AM PDT 24 |
Jul 02 09:59:59 AM PDT 24 |
24754900 ps |
| T312 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.1773142655 |
|
|
Jul 02 10:00:00 AM PDT 24 |
Jul 02 10:00:38 AM PDT 24 |
185167500 ps |
| T1194 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.2566938889 |
|
|
Jul 02 09:59:53 AM PDT 24 |
Jul 02 10:00:10 AM PDT 24 |
48213700 ps |
| T1195 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.3507862889 |
|
|
Jul 02 09:59:55 AM PDT 24 |
Jul 02 10:00:22 AM PDT 24 |
74256600 ps |
| T1196 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3977046089 |
|
|
Jul 02 09:59:33 AM PDT 24 |
Jul 02 10:00:14 AM PDT 24 |
339377900 ps |
| T1197 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.1873270984 |
|
|
Jul 02 09:59:37 AM PDT 24 |
Jul 02 09:59:53 AM PDT 24 |
116047800 ps |
| T1198 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.3029482912 |
|
|
Jul 02 09:59:35 AM PDT 24 |
Jul 02 09:59:51 AM PDT 24 |
18911400 ps |
| T1199 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.2911530529 |
|
|
Jul 02 09:59:33 AM PDT 24 |
Jul 02 09:59:49 AM PDT 24 |
23305400 ps |
| T1200 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2484493345 |
|
|
Jul 02 10:00:00 AM PDT 24 |
Jul 02 10:00:18 AM PDT 24 |
175988900 ps |
| T1201 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.452971308 |
|
|
Jul 02 09:59:48 AM PDT 24 |
Jul 02 10:00:08 AM PDT 24 |
87293500 ps |
| T1202 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.2197823143 |
|
|
Jul 02 09:59:50 AM PDT 24 |
Jul 02 10:00:08 AM PDT 24 |
33300900 ps |
| T1203 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3380205164 |
|
|
Jul 02 09:59:55 AM PDT 24 |
Jul 02 10:00:16 AM PDT 24 |
253852300 ps |
| T1204 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2466980830 |
|
|
Jul 02 09:59:42 AM PDT 24 |
Jul 02 10:00:03 AM PDT 24 |
215693700 ps |
| T1205 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.4293643557 |
|
|
Jul 02 10:00:01 AM PDT 24 |
Jul 02 10:00:18 AM PDT 24 |
51257400 ps |
| T1206 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.3504882078 |
|
|
Jul 02 09:59:40 AM PDT 24 |
Jul 02 09:59:58 AM PDT 24 |
13681100 ps |
| T1207 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.163843323 |
|
|
Jul 02 09:59:59 AM PDT 24 |
Jul 02 10:00:20 AM PDT 24 |
70016500 ps |
| T1208 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.3425642161 |
|
|
Jul 02 09:59:57 AM PDT 24 |
Jul 02 10:00:35 AM PDT 24 |
293163600 ps |
| T1209 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.2730236642 |
|
|
Jul 02 09:59:46 AM PDT 24 |
Jul 02 10:00:00 AM PDT 24 |
29449000 ps |
| T1210 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.2938055765 |
|
|
Jul 02 09:59:47 AM PDT 24 |
Jul 02 10:07:27 AM PDT 24 |
772544600 ps |
| T1211 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.3426299684 |
|
|
Jul 02 09:59:49 AM PDT 24 |
Jul 02 10:00:07 AM PDT 24 |
98008600 ps |
| T1212 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.1391987012 |
|
|
Jul 02 09:59:56 AM PDT 24 |
Jul 02 10:00:12 AM PDT 24 |
10861500 ps |
| T1213 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.288481496 |
|
|
Jul 02 09:59:44 AM PDT 24 |
Jul 02 10:00:25 AM PDT 24 |
617077000 ps |
| T313 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.4231024037 |
|
|
Jul 02 09:59:53 AM PDT 24 |
Jul 02 10:00:32 AM PDT 24 |
813704000 ps |
| T1214 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.3493715652 |
|
|
Jul 02 09:59:53 AM PDT 24 |
Jul 02 10:00:15 AM PDT 24 |
693270000 ps |
| T1215 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.1399466652 |
|
|
Jul 02 09:59:48 AM PDT 24 |
Jul 02 10:00:08 AM PDT 24 |
115900700 ps |
| T351 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.434060211 |
|
|
Jul 02 09:59:38 AM PDT 24 |
Jul 02 10:14:41 AM PDT 24 |
882527800 ps |
| T1216 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2984543788 |
|
|
Jul 02 09:59:43 AM PDT 24 |
Jul 02 10:00:01 AM PDT 24 |
42201500 ps |
| T1217 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.2508886159 |
|
|
Jul 02 09:59:48 AM PDT 24 |
Jul 02 10:00:03 AM PDT 24 |
31672800 ps |
| T356 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.4102070330 |
|
|
Jul 02 09:59:41 AM PDT 24 |
Jul 02 10:14:37 AM PDT 24 |
3279342000 ps |
| T1218 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.2414939093 |
|
|
Jul 02 09:59:54 AM PDT 24 |
Jul 02 10:00:13 AM PDT 24 |
22975700 ps |
| T1219 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1969842242 |
|
|
Jul 02 09:59:53 AM PDT 24 |
Jul 02 10:00:12 AM PDT 24 |
78457900 ps |
| T1220 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1933759824 |
|
|
Jul 02 09:59:51 AM PDT 24 |
Jul 02 10:00:08 AM PDT 24 |
44687500 ps |
| T1221 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.1601647676 |
|
|
Jul 02 09:59:33 AM PDT 24 |
Jul 02 10:00:06 AM PDT 24 |
68618000 ps |
| T1222 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.3372267286 |
|
|
Jul 02 09:59:26 AM PDT 24 |
Jul 02 09:59:43 AM PDT 24 |
34621000 ps |
| T1223 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3153613309 |
|
|
Jul 02 09:59:51 AM PDT 24 |
Jul 02 10:00:09 AM PDT 24 |
24053600 ps |
| T1224 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1575708415 |
|
|
Jul 02 09:59:59 AM PDT 24 |
Jul 02 10:00:16 AM PDT 24 |
136826300 ps |
| T1225 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1493374455 |
|
|
Jul 02 09:59:34 AM PDT 24 |
Jul 02 10:00:08 AM PDT 24 |
2191041100 ps |
| T1226 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.2721314506 |
|
|
Jul 02 09:59:44 AM PDT 24 |
Jul 02 09:59:59 AM PDT 24 |
27548200 ps |
| T1227 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.922852133 |
|
|
Jul 02 10:00:06 AM PDT 24 |
Jul 02 10:00:25 AM PDT 24 |
44088600 ps |
| T1228 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.774708022 |
|
|
Jul 02 09:59:31 AM PDT 24 |
Jul 02 09:59:52 AM PDT 24 |
44995700 ps |
| T1229 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3713014587 |
|
|
Jul 02 09:59:39 AM PDT 24 |
Jul 02 09:59:58 AM PDT 24 |
62520000 ps |
| T1230 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.2119127983 |
|
|
Jul 02 09:59:38 AM PDT 24 |
Jul 02 09:59:55 AM PDT 24 |
56940900 ps |
| T1231 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3421875594 |
|
|
Jul 02 09:59:47 AM PDT 24 |
Jul 02 10:00:43 AM PDT 24 |
901702400 ps |
| T1232 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.2590368402 |
|
|
Jul 02 10:00:11 AM PDT 24 |
Jul 02 10:00:29 AM PDT 24 |
17465300 ps |
| T1233 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1144436356 |
|
|
Jul 02 09:59:53 AM PDT 24 |
Jul 02 10:00:12 AM PDT 24 |
13762200 ps |
| T245 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.3598790318 |
|
|
Jul 02 09:59:36 AM PDT 24 |
Jul 02 09:59:53 AM PDT 24 |
63749200 ps |
| T349 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1354824732 |
|
|
Jul 02 09:59:52 AM PDT 24 |
Jul 02 10:00:15 AM PDT 24 |
68916200 ps |
| T1234 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.3752413527 |
|
|
Jul 02 09:59:53 AM PDT 24 |
Jul 02 10:00:09 AM PDT 24 |
24429600 ps |
| T1235 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.3849952365 |
|
|
Jul 02 09:59:58 AM PDT 24 |
Jul 02 10:00:14 AM PDT 24 |
72270000 ps |
| T1236 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.2843121470 |
|
|
Jul 02 09:59:47 AM PDT 24 |
Jul 02 10:00:06 AM PDT 24 |
39607800 ps |
| T1237 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.2295239599 |
|
|
Jul 02 09:59:30 AM PDT 24 |
Jul 02 09:59:48 AM PDT 24 |
19527900 ps |
| T1238 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.925275929 |
|
|
Jul 02 09:59:48 AM PDT 24 |
Jul 02 10:00:06 AM PDT 24 |
82541100 ps |
| T1239 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1692477719 |
|
|
Jul 02 09:59:33 AM PDT 24 |
Jul 02 09:59:54 AM PDT 24 |
54242200 ps |
| T1240 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.2632772393 |
|
|
Jul 02 09:59:52 AM PDT 24 |
Jul 02 10:00:08 AM PDT 24 |
11344900 ps |
| T1241 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3630851124 |
|
|
Jul 02 09:59:43 AM PDT 24 |
Jul 02 10:00:35 AM PDT 24 |
1710867900 ps |
| T1242 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1259670101 |
|
|
Jul 02 09:59:53 AM PDT 24 |
Jul 02 10:00:11 AM PDT 24 |
472590000 ps |
| T1243 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.529309260 |
|
|
Jul 02 10:00:02 AM PDT 24 |
Jul 02 10:00:23 AM PDT 24 |
21449400 ps |
| T1244 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.1405532818 |
|
|
Jul 02 09:59:48 AM PDT 24 |
Jul 02 10:00:36 AM PDT 24 |
47545800 ps |
| T1245 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.3205971410 |
|
|
Jul 02 09:59:48 AM PDT 24 |
Jul 02 10:00:03 AM PDT 24 |
29324100 ps |
| T1246 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.654856822 |
|
|
Jul 02 10:00:03 AM PDT 24 |
Jul 02 10:00:26 AM PDT 24 |
81621100 ps |
| T1247 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.794262361 |
|
|
Jul 02 09:59:54 AM PDT 24 |
Jul 02 10:00:12 AM PDT 24 |
14225400 ps |
| T1248 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3166686480 |
|
|
Jul 02 09:59:42 AM PDT 24 |
Jul 02 10:00:04 AM PDT 24 |
118802100 ps |
| T1249 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.1042150400 |
|
|
Jul 02 09:59:32 AM PDT 24 |
Jul 02 09:59:53 AM PDT 24 |
104054600 ps |
| T1250 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.640743952 |
|
|
Jul 02 09:59:38 AM PDT 24 |
Jul 02 10:00:15 AM PDT 24 |
123454000 ps |
| T1251 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.3824561846 |
|
|
Jul 02 09:59:43 AM PDT 24 |
Jul 02 10:00:03 AM PDT 24 |
54983800 ps |
| T1252 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.2774838559 |
|
|
Jul 02 09:59:48 AM PDT 24 |
Jul 02 10:00:03 AM PDT 24 |
142484900 ps |
| T1253 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.3038879558 |
|
|
Jul 02 09:59:37 AM PDT 24 |
Jul 02 09:59:54 AM PDT 24 |
32749900 ps |