Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	353640	1		T1	1		T2	2		T3	1
all_values[1]	353640	1		T1	1		T2	2		T3	1
all_values[2]	353640	1		T1	1		T2	2		T3	1
all_values[3]	353640	1		T1	1		T2	2		T3	1
all_values[4]	353640	1		T1	1		T2	2		T3	1
all_values[5]	353640	1		T1	1		T2	2		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	713638	1		T1	6		T2	12		T3	6
auto[1]	1408202	1		T4	25540		T23	1088		T22	12608

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1041696	1		T1	4		T2	7		T3	4
auto[1]	1080144	1		T1	2		T2	5		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	353479	1		T1	1		T2	2		T3	1
all_values[0]	auto[1]	auto[1]	161	1		T260	4		T261	3		T262	6
all_values[1]	auto[0]	auto[1]	353493	1		T1	1		T2	2		T3	1
all_values[1]	auto[1]	auto[1]	147	1		T260	3		T261	1		T262	4
all_values[2]	auto[0]	auto[0]	1604	1		T1	1		T2	2		T3	1
all_values[2]	auto[0]	auto[1]	67	1		T260	1		T327	1		T325	1
all_values[2]	auto[1]	auto[0]	351913	1		T4	6385		T23	272		T22	3152
all_values[2]	auto[1]	auto[1]	56	1		T261	4		T262	2		T339	1
all_values[3]	auto[0]	auto[0]	1599	1		T1	1		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	60	1		T260	2		T261	1		T262	3
all_values[3]	auto[1]	auto[0]	87806	1		T4	23		T23	68		T22	1576
all_values[3]	auto[1]	auto[1]	264175	1		T4	6362		T23	204		T22	1576
all_values[4]	auto[0]	auto[0]	1122	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	531	1		T2	1		T5	1		T7	1
all_values[4]	auto[1]	auto[0]	244188	1		T4	5812		T23	204		T22	1576
all_values[4]	auto[1]	auto[1]	107799	1		T4	573		T23	68		T22	1576
all_values[5]	auto[0]	auto[0]	1583	1		T1	1		T2	2		T3	1
all_values[5]	auto[0]	auto[1]	100	1		T34	1		T35	1		T36	1
all_values[5]	auto[1]	auto[0]	351881	1		T4	6385		T23	272		T22	3152
all_values[5]	auto[1]	auto[1]	76	1		T261	1		T262	1		T327	1