Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	1	15	93.75

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	1	15	93.75	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	243333	1		T2	41		T3	1		T4	322
auto[FlashEraseBank]	274521	1		T1	1		T2	9		T4	251

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	259309	1		T2	50		T3	1		T4	573
auto[FlashOpProgram]	238834	1		T1	1		T16	1		T5	1
auto[FlashOpErase]	15711	1		T5	1		T6	220		T7	3
auto[FlashOpInvalid]	4000	1		T272	200		T273	200		T274	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	259309	1		T2	50		T3	1		T4	573
op[FlashOpProgram]	238834	1		T1	1		T16	1		T5	1
op[FlashOpErase]	15711	1		T5	1		T6	220		T7	3
read_erase_read	549	1		T17	6		T69	2		T29	2
read_prog_read	939	1		T16	1		T17	18		T42	7

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	376922	1		T2	50		T16	1		T5	2
auto[FlashPartInfo]	137217	1		T1	1		T3	1		T4	573
auto[FlashPartInfo1]	839	1		T19	64		T42	1		T35	4
auto[FlashPartInfo2]	2876	1		T19	128		T42	14		T23	68

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for op_part_cross

Uncovered bins

part_cp	op_cp	COUNT	AT LEAST	NUMBER
[auto[FlashPartInfo1]]	[auto[FlashOpInvalid]]	0	1	1

Covered bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	188374	1		T2	50		T16	1		T7	5
auto[FlashPartData]	auto[FlashOpProgram]	181087	1		T5	1		T7	9		T17	82
auto[FlashPartData]	auto[FlashOpErase]	3541	1		T5	1		T7	3		T17	26
auto[FlashPartData]	auto[FlashOpInvalid]	3920	1		T272	190		T273	198		T274	194
auto[FlashPartInfo]	auto[FlashOpRead]	68363	1		T3	1		T4	573		T16	8
auto[FlashPartInfo]	auto[FlashOpProgram]	56638	1		T1	1		T16	1		T6	220
auto[FlashPartInfo]	auto[FlashOpErase]	12142	1		T6	220		T39	285		T60	261
auto[FlashPartInfo]	auto[FlashOpInvalid]	74	1		T272	10		T273	2		T274	6
auto[FlashPartInfo1]	auto[FlashOpRead]	674	1		T19	32		T42	1		T35	4
auto[FlashPartInfo1]	auto[FlashOpProgram]	163	1		T19	32		T226	1		T125	32
auto[FlashPartInfo1]	auto[FlashOpErase]	2	1		T68	1		T123	1		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1898	1		T19	64		T42	8		T23	68
auto[FlashPartInfo2]	auto[FlashOpProgram]	946	1		T19	64		T42	6		T35	9
auto[FlashPartInfo2]	auto[FlashOpErase]	26	1		T120	1		T215	1		T148	4
auto[FlashPartInfo2]	auto[FlashOpInvalid]	6	1		T344	2		T345	2		T346	2