Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31015	1		T6	440		T7	4		T17	20
auto[1]	42	1		T75	2		T208	1		T76	4
auto[2]	79	1		T24	1		T139	4		T175	8
auto[3]	237	1		T21	1		T24	1		T206	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7850	1		T6	110		T7	1		T17	5
evic_idx[1]	7862	1		T6	110		T7	1		T17	5
evic_idx[2]	7830	1		T6	110		T7	1		T17	5
evic_idx[3]	7831	1		T6	110		T7	1		T17	5

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Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	30416	1		T6	440		T39	556		T60	520
evic_op[2]	328	1		T21	1		T75	2		T70	16

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7539	1		T6	110		T39	139		T60	130
evic_idx[0]	evic_op[1]	auto[1]	7	1		T215	2		T393	4		T394	1
evic_idx[0]	evic_op[1]	auto[2]	12	1		T395	2		T396	1		T397	6
evic_idx[0]	evic_op[1]	auto[3]	46	1		T140	4		T215	4		T398	7
evic_idx[0]	evic_op[2]	auto[0]	63	1		T70	4		T206	1		T120	1
evic_idx[0]	evic_op[2]	auto[1]	4	1		T76	1		T77	1		T399	1
evic_idx[0]	evic_op[2]	auto[2]	4	1		T400	1		T401	1		T402	1
evic_idx[0]	evic_op[2]	auto[3]	17	1		T21	1		T206	1		T38	1
evic_idx[1]	evic_op[1]	auto[0]	7540	1		T6	110		T39	139		T60	130
evic_idx[1]	evic_op[1]	auto[1]	6	1		T215	2		T214	1		T393	2
evic_idx[1]	evic_op[1]	auto[2]	10	1		T395	2		T403	1		T396	2
evic_idx[1]	evic_op[1]	auto[3]	66	1		T140	5		T215	6		T398	7
evic_idx[1]	evic_op[2]	auto[0]	63	1		T70	4		T120	1		T211	8
evic_idx[1]	evic_op[2]	auto[1]	5	1		T76	1		T77	1		T404	1
evic_idx[1]	evic_op[2]	auto[2]	3	1		T405	2		T406	1		-	-
evic_idx[1]	evic_op[2]	auto[3]	11	1		T24	1		T137	1		T112	1
evic_idx[2]	evic_op[1]	auto[0]	7539	1		T6	110		T39	139		T60	130
evic_idx[2]	evic_op[1]	auto[1]	4	1		T215	2		T393	1		T394	1
evic_idx[2]	evic_op[1]	auto[2]	8	1		T396	2		T397	5		T407	1
evic_idx[2]	evic_op[1]	auto[3]	47	1		T140	2		T215	6		T395	1
evic_idx[2]	evic_op[2]	auto[0]	64	1		T70	4		T223	1		T120	1
evic_idx[2]	evic_op[2]	auto[1]	5	1		T208	1		T76	1		T77	1
evic_idx[2]	evic_op[2]	auto[2]	1	1		T405	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[3]	5	1		T408	1		T409	1		T410	1
evic_idx[3]	evic_op[1]	auto[0]	7542	1		T6	110		T39	139		T60	130
evic_idx[3]	evic_op[1]	auto[1]	5	1		T215	2		T393	1		T394	2
evic_idx[3]	evic_op[1]	auto[2]	9	1		T395	1		T396	1		T397	4
evic_idx[3]	evic_op[1]	auto[3]	36	1		T140	4		T215	3		T398	4
evic_idx[3]	evic_op[2]	auto[0]	64	1		T70	4		T120	1		T211	8
evic_idx[3]	evic_op[2]	auto[1]	6	1		T75	2		T76	1		T77	1
evic_idx[3]	evic_op[2]	auto[2]	4	1		T24	1		T404	1		T405	1
evic_idx[3]	evic_op[2]	auto[3]	9	1		T411	1		T412	1		T413	1