Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	34330	1		T4	2054		T222	2627		T333	14674
rd_lvl[2]	50168	1		T4	1001		T222	2111		T334	13092
rd_lvl[3]	20866	1		T4	430		T222	1153		T334	634
rd_lvl[4]	33233	1		T4	474		T222	1094		T335	3891
rd_lvl[5]	9188	1		T4	176		T23	147		T222	924
rd_lvl[6]	14308	1		T4	109		T23	57		T222	9
rd_lvl[7]	14551	1		T4	133		T174	1927		T222	892
rd_lvl[8]	16654	1		T4	171		T174	1507		T222	890
rd_lvl[9]	4322	1		T4	200		T222	1169		T129	616
rd_lvl[10]	5461	1		T4	61		T222	611		T129	1103
rd_lvl[11]	3253	1		T4	288		T222	15		T205	174
rd_lvl[12]	9155	1		T4	1		T205	1607		T33	201
rd_lvl[13]	2559	1		T4	2		T336	333		T337	1
rd_lvl[14]	6080	1		T4	130		T222	15		T33	36
rd_lvl[15]	2413	1		T22	532		T32	178		T338	269