Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	353640	1		T1	1		T2	2		T3	1
all_pins[1]	353640	1		T1	1		T2	2		T3	1
all_pins[2]	353640	1		T1	1		T2	2		T3	1
all_pins[3]	353640	1		T1	1		T2	2		T3	1
all_pins[4]	353640	1		T1	1		T2	2		T3	1
all_pins[5]	353640	1		T1	1		T2	2		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1768989	1		T1	6		T2	12		T3	6
values[0x1]	352851	1		T4	5834		T23	289		T22	5240
transitions[0x0=>0x1]	319158	1		T4	5253		T23	272		T22	3152
transitions[0x1=>0x0]	319144	1		T4	5253		T23	272		T22	3152

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	353479	1		T1	1		T2	2		T3	1
all_pins[0]	values[0x1]	161	1		T260	4		T261	3		T262	6
all_pins[0]	transitions[0x0=>0x1]	98	1		T260	2		T261	2		T262	3
all_pins[0]	transitions[0x1=>0x0]	84	1		T260	1		T262	1		T327	1
all_pins[1]	values[0x0]	353493	1		T1	1		T2	2		T3	1
all_pins[1]	values[0x1]	147	1		T260	3		T261	1		T262	4
all_pins[1]	transitions[0x0=>0x1]	121	1		T260	3		T262	3		T327	4
all_pins[1]	transitions[0x1=>0x0]	4207	1		T22	1044		T32	106		T338	256
all_pins[2]	values[0x0]	349407	1		T1	1		T2	2		T3	1
all_pins[2]	values[0x1]	4233	1		T22	1044		T32	106		T338	256
all_pins[2]	transitions[0x0=>0x1]	42	1		T261	3		T262	2		T328	1
all_pins[2]	transitions[0x1=>0x0]	226822	1		T4	5230		T23	204		T22	532
all_pins[3]	values[0x0]	122627	1		T1	1		T2	2		T3	1
all_pins[3]	values[0x1]	231013	1		T4	5230		T23	204		T22	1576
all_pins[3]	transitions[0x0=>0x1]	201659	1		T4	4649		T23	187		T22	532
all_pins[3]	transitions[0x1=>0x0]	87867	1		T4	23		T23	68		T22	1576
all_pins[4]	values[0x0]	236419	1		T1	1		T2	2		T3	1
all_pins[4]	values[0x1]	117221	1		T4	604		T23	85		T22	2620
all_pins[4]	transitions[0x0=>0x1]	117199	1		T4	604		T23	85		T22	2620
all_pins[4]	transitions[0x1=>0x0]	54	1		T261	1		T332	5		T330	2
all_pins[5]	values[0x0]	353564	1		T1	1		T2	2		T3	1
all_pins[5]	values[0x1]	76	1		T261	1		T262	1		T327	1
all_pins[5]	transitions[0x0=>0x1]	39	1		T262	1		T325	2		T332	3
all_pins[5]	transitions[0x1=>0x0]	110	1		T260	4		T261	3		T262	5