| T1078 |
/workspace/coverage/default/23.flash_ctrl_disable.2036128744 |
|
|
Jul 03 05:13:19 PM PDT 24 |
Jul 03 05:13:42 PM PDT 24 |
12104100 ps |
| T407 |
/workspace/coverage/default/9.flash_ctrl_re_evict.882060233 |
|
|
Jul 03 05:11:05 PM PDT 24 |
Jul 03 05:11:39 PM PDT 24 |
746931100 ps |
| T1079 |
/workspace/coverage/default/7.flash_ctrl_rw_evict.110289592 |
|
|
Jul 03 05:10:26 PM PDT 24 |
Jul 03 05:10:58 PM PDT 24 |
27992400 ps |
| T1080 |
/workspace/coverage/default/8.flash_ctrl_alert_test.1510825499 |
|
|
Jul 03 05:10:43 PM PDT 24 |
Jul 03 05:10:57 PM PDT 24 |
72881800 ps |
| T1081 |
/workspace/coverage/default/0.flash_ctrl_sec_info_access.1722277535 |
|
|
Jul 03 05:08:28 PM PDT 24 |
Jul 03 05:09:29 PM PDT 24 |
1317890900 ps |
| T180 |
/workspace/coverage/default/3.flash_ctrl_mid_op_rst.1103398162 |
|
|
Jul 03 05:08:56 PM PDT 24 |
Jul 03 05:10:11 PM PDT 24 |
657390800 ps |
| T1082 |
/workspace/coverage/default/47.flash_ctrl_disable.703946293 |
|
|
Jul 03 05:15:21 PM PDT 24 |
Jul 03 05:15:44 PM PDT 24 |
31699400 ps |
| T1083 |
/workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.391058893 |
|
|
Jul 03 05:12:31 PM PDT 24 |
Jul 03 05:15:03 PM PDT 24 |
10012134100 ps |
| T1084 |
/workspace/coverage/default/13.flash_ctrl_smoke.3770217971 |
|
|
Jul 03 05:11:37 PM PDT 24 |
Jul 03 05:14:07 PM PDT 24 |
1415236200 ps |
| T1085 |
/workspace/coverage/default/16.flash_ctrl_prog_reset.1902665290 |
|
|
Jul 03 05:12:23 PM PDT 24 |
Jul 03 05:12:37 PM PDT 24 |
32366800 ps |
| T1086 |
/workspace/coverage/default/38.flash_ctrl_hw_sec_otp.800219501 |
|
|
Jul 03 05:14:33 PM PDT 24 |
Jul 03 05:16:27 PM PDT 24 |
7368736200 ps |
| T1087 |
/workspace/coverage/default/30.flash_ctrl_rw_evict.3845786378 |
|
|
Jul 03 05:13:57 PM PDT 24 |
Jul 03 05:14:29 PM PDT 24 |
46893100 ps |
| T221 |
/workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.3782712145 |
|
|
Jul 03 05:09:22 PM PDT 24 |
Jul 03 05:09:36 PM PDT 24 |
24559000 ps |
| T1088 |
/workspace/coverage/default/1.flash_ctrl_rw_evict_all_en.1200826521 |
|
|
Jul 03 05:08:43 PM PDT 24 |
Jul 03 05:09:15 PM PDT 24 |
27588600 ps |
| T1089 |
/workspace/coverage/default/12.flash_ctrl_alert_test.2016566074 |
|
|
Jul 03 05:11:37 PM PDT 24 |
Jul 03 05:11:51 PM PDT 24 |
24171300 ps |
| T1090 |
/workspace/coverage/default/7.flash_ctrl_hw_read_seed_err.3963433985 |
|
|
Jul 03 05:10:28 PM PDT 24 |
Jul 03 05:10:42 PM PDT 24 |
47856400 ps |
| T1091 |
/workspace/coverage/default/33.flash_ctrl_sec_info_access.3717195137 |
|
|
Jul 03 05:14:11 PM PDT 24 |
Jul 03 05:15:24 PM PDT 24 |
3195534000 ps |
| T1092 |
/workspace/coverage/default/20.flash_ctrl_intr_rd_slow_flash.2903136702 |
|
|
Jul 03 05:13:04 PM PDT 24 |
Jul 03 05:15:15 PM PDT 24 |
6000138600 ps |
| T1093 |
/workspace/coverage/default/32.flash_ctrl_intr_rd.433362303 |
|
|
Jul 03 05:14:07 PM PDT 24 |
Jul 03 05:18:21 PM PDT 24 |
4046266800 ps |
| T1094 |
/workspace/coverage/default/10.flash_ctrl_sec_info_access.787296496 |
|
|
Jul 03 05:11:21 PM PDT 24 |
Jul 03 05:12:35 PM PDT 24 |
5696012200 ps |
| T46 |
/workspace/coverage/default/0.flash_ctrl_access_after_disable.1684597725 |
|
|
Jul 03 05:08:38 PM PDT 24 |
Jul 03 05:08:52 PM PDT 24 |
14919800 ps |
| T1095 |
/workspace/coverage/default/8.flash_ctrl_hw_rma_reset.3675099221 |
|
|
Jul 03 05:10:34 PM PDT 24 |
Jul 03 05:25:43 PM PDT 24 |
80146121300 ps |
| T1096 |
/workspace/coverage/default/0.flash_ctrl_rd_intg.4058352497 |
|
|
Jul 03 05:08:33 PM PDT 24 |
Jul 03 05:09:03 PM PDT 24 |
63289600 ps |
| T1097 |
/workspace/coverage/default/49.flash_ctrl_hw_sec_otp.1044612326 |
|
|
Jul 03 05:15:28 PM PDT 24 |
Jul 03 05:17:09 PM PDT 24 |
2221546300 ps |
| T56 |
/workspace/coverage/default/5.flash_ctrl_fetch_code.1731263338 |
|
|
Jul 03 05:09:48 PM PDT 24 |
Jul 03 05:10:09 PM PDT 24 |
229858100 ps |
| T1098 |
/workspace/coverage/default/1.flash_ctrl_smoke_hw.794303345 |
|
|
Jul 03 05:08:35 PM PDT 24 |
Jul 03 05:09:02 PM PDT 24 |
65430700 ps |
| T1099 |
/workspace/coverage/default/7.flash_ctrl_ro_serr.749368132 |
|
|
Jul 03 05:10:25 PM PDT 24 |
Jul 03 05:12:52 PM PDT 24 |
7016185600 ps |
| T1100 |
/workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.2900306664 |
|
|
Jul 03 05:11:29 PM PDT 24 |
Jul 03 05:12:00 PM PDT 24 |
41642000 ps |
| T1101 |
/workspace/coverage/default/6.flash_ctrl_hw_read_seed_err.981574760 |
|
|
Jul 03 05:10:10 PM PDT 24 |
Jul 03 05:10:24 PM PDT 24 |
45725800 ps |
| T1102 |
/workspace/coverage/default/12.flash_ctrl_lcmgr_intg.3307204034 |
|
|
Jul 03 05:11:34 PM PDT 24 |
Jul 03 05:11:48 PM PDT 24 |
24728000 ps |
| T1103 |
/workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.2391821823 |
|
|
Jul 03 05:09:22 PM PDT 24 |
Jul 03 05:10:24 PM PDT 24 |
10032559200 ps |
| T1104 |
/workspace/coverage/default/13.flash_ctrl_prog_reset.3774877158 |
|
|
Jul 03 05:11:45 PM PDT 24 |
Jul 03 05:12:00 PM PDT 24 |
111088000 ps |
| T1105 |
/workspace/coverage/default/4.flash_ctrl_intr_wr.3273270189 |
|
|
Jul 03 05:09:38 PM PDT 24 |
Jul 03 05:10:43 PM PDT 24 |
2196100700 ps |
| T181 |
/workspace/coverage/default/1.flash_ctrl_mid_op_rst.2988334653 |
|
|
Jul 03 05:08:40 PM PDT 24 |
Jul 03 05:09:55 PM PDT 24 |
2906558400 ps |
| T1106 |
/workspace/coverage/default/47.flash_ctrl_sec_info_access.2436427605 |
|
|
Jul 03 05:15:22 PM PDT 24 |
Jul 03 05:16:44 PM PDT 24 |
8961322000 ps |
| T314 |
/workspace/coverage/default/41.flash_ctrl_hw_sec_otp.3045212010 |
|
|
Jul 03 05:14:44 PM PDT 24 |
Jul 03 05:17:19 PM PDT 24 |
8749697400 ps |
| T1107 |
/workspace/coverage/default/16.flash_ctrl_otp_reset.3283733920 |
|
|
Jul 03 05:12:18 PM PDT 24 |
Jul 03 05:14:35 PM PDT 24 |
142420600 ps |
| T1108 |
/workspace/coverage/default/73.flash_ctrl_otp_reset.4293335953 |
|
|
Jul 03 05:15:51 PM PDT 24 |
Jul 03 05:18:06 PM PDT 24 |
114215700 ps |
| T1109 |
/workspace/coverage/default/67.flash_ctrl_otp_reset.4233518829 |
|
|
Jul 03 05:15:42 PM PDT 24 |
Jul 03 05:17:58 PM PDT 24 |
202657300 ps |
| T260 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.2474051088 |
|
|
Jul 03 07:10:14 PM PDT 24 |
Jul 03 07:10:47 PM PDT 24 |
55565700 ps |
| T261 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.3580767225 |
|
|
Jul 03 07:10:05 PM PDT 24 |
Jul 03 07:10:32 PM PDT 24 |
16399600 ps |
| T62 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.3664827543 |
|
|
Jul 03 07:10:08 PM PDT 24 |
Jul 03 07:10:41 PM PDT 24 |
630350100 ps |
| T63 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.3691294968 |
|
|
Jul 03 07:09:52 PM PDT 24 |
Jul 03 07:24:59 PM PDT 24 |
752082300 ps |
| T262 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.3693122994 |
|
|
Jul 03 07:10:22 PM PDT 24 |
Jul 03 07:10:57 PM PDT 24 |
17934500 ps |
| T64 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.4041269421 |
|
|
Jul 03 07:09:55 PM PDT 24 |
Jul 03 07:10:25 PM PDT 24 |
85904400 ps |
| T94 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1155211649 |
|
|
Jul 03 07:10:07 PM PDT 24 |
Jul 03 07:10:40 PM PDT 24 |
223619200 ps |
| T249 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.1050310979 |
|
|
Jul 03 07:09:54 PM PDT 24 |
Jul 03 07:10:21 PM PDT 24 |
53450700 ps |
| T1110 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.3328349076 |
|
|
Jul 03 07:10:03 PM PDT 24 |
Jul 03 07:10:32 PM PDT 24 |
25066700 ps |
| T253 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.2045700409 |
|
|
Jul 03 07:09:52 PM PDT 24 |
Jul 03 07:10:17 PM PDT 24 |
29968000 ps |
| T194 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1148656641 |
|
|
Jul 03 07:07:01 PM PDT 24 |
Jul 03 07:07:42 PM PDT 24 |
6792629600 ps |
| T251 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1663624915 |
|
|
Jul 03 07:09:35 PM PDT 24 |
Jul 03 07:10:01 PM PDT 24 |
137884500 ps |
| T250 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2436643801 |
|
|
Jul 03 07:09:36 PM PDT 24 |
Jul 03 07:10:54 PM PDT 24 |
7058174500 ps |
| T192 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.443935633 |
|
|
Jul 03 07:09:34 PM PDT 24 |
Jul 03 07:24:46 PM PDT 24 |
3268767600 ps |
| T252 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1894055187 |
|
|
Jul 03 07:07:06 PM PDT 24 |
Jul 03 07:07:48 PM PDT 24 |
645825400 ps |
| T1111 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3340715352 |
|
|
Jul 03 07:10:11 PM PDT 24 |
Jul 03 07:10:47 PM PDT 24 |
131931800 ps |
| T1112 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1389866836 |
|
|
Jul 03 07:09:36 PM PDT 24 |
Jul 03 07:10:00 PM PDT 24 |
54691200 ps |
| T191 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.1825670498 |
|
|
Jul 03 07:09:54 PM PDT 24 |
Jul 03 07:10:23 PM PDT 24 |
171629200 ps |
| T1113 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.4087617091 |
|
|
Jul 03 07:09:33 PM PDT 24 |
Jul 03 07:09:54 PM PDT 24 |
15974800 ps |
| T1114 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3079073404 |
|
|
Jul 03 07:09:50 PM PDT 24 |
Jul 03 07:10:12 PM PDT 24 |
25457700 ps |
| T230 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3213388819 |
|
|
Jul 03 07:09:54 PM PDT 24 |
Jul 03 07:10:24 PM PDT 24 |
46562500 ps |
| T254 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.2465455834 |
|
|
Jul 03 07:07:14 PM PDT 24 |
Jul 03 07:08:45 PM PDT 24 |
5050201600 ps |
| T327 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.3155673967 |
|
|
Jul 03 07:10:11 PM PDT 24 |
Jul 03 07:10:43 PM PDT 24 |
86644800 ps |
| T1115 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.2106490116 |
|
|
Jul 03 07:09:34 PM PDT 24 |
Jul 03 07:10:01 PM PDT 24 |
154827400 ps |
| T1116 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1199116820 |
|
|
Jul 03 07:09:56 PM PDT 24 |
Jul 03 07:10:24 PM PDT 24 |
71786100 ps |
| T1117 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.4107999796 |
|
|
Jul 03 07:09:54 PM PDT 24 |
Jul 03 07:10:40 PM PDT 24 |
61992000 ps |
| T231 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1675950025 |
|
|
Jul 03 07:09:33 PM PDT 24 |
Jul 03 07:09:56 PM PDT 24 |
26665900 ps |
| T325 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.2034446231 |
|
|
Jul 03 07:10:14 PM PDT 24 |
Jul 03 07:10:47 PM PDT 24 |
136995900 ps |
| T326 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.731465519 |
|
|
Jul 03 07:10:10 PM PDT 24 |
Jul 03 07:10:42 PM PDT 24 |
30968500 ps |
| T193 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.461636666 |
|
|
Jul 03 07:09:55 PM PDT 24 |
Jul 03 07:17:49 PM PDT 24 |
560590700 ps |
| T339 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.4080642854 |
|
|
Jul 03 07:10:21 PM PDT 24 |
Jul 03 07:10:57 PM PDT 24 |
55578300 ps |
| T332 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.3546731998 |
|
|
Jul 03 07:09:34 PM PDT 24 |
Jul 03 07:09:54 PM PDT 24 |
48130400 ps |
| T1118 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.1970868696 |
|
|
Jul 03 07:09:39 PM PDT 24 |
Jul 03 07:10:00 PM PDT 24 |
21014900 ps |
| T292 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.1604277207 |
|
|
Jul 03 07:10:15 PM PDT 24 |
Jul 03 07:10:53 PM PDT 24 |
823744100 ps |
| T1119 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.3413831582 |
|
|
Jul 03 07:09:37 PM PDT 24 |
Jul 03 07:10:43 PM PDT 24 |
636906500 ps |
| T330 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2934237441 |
|
|
Jul 03 07:10:15 PM PDT 24 |
Jul 03 07:10:48 PM PDT 24 |
15512400 ps |
| T1120 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.2880665692 |
|
|
Jul 03 07:10:07 PM PDT 24 |
Jul 03 07:10:40 PM PDT 24 |
29844400 ps |
| T232 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2000183743 |
|
|
Jul 03 07:09:50 PM PDT 24 |
Jul 03 07:10:13 PM PDT 24 |
128063700 ps |
| T293 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3684242924 |
|
|
Jul 03 07:09:35 PM PDT 24 |
Jul 03 07:10:00 PM PDT 24 |
378269600 ps |
| T1121 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.4062063050 |
|
|
Jul 03 07:09:55 PM PDT 24 |
Jul 03 07:10:20 PM PDT 24 |
64557300 ps |
| T328 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.128405060 |
|
|
Jul 03 07:10:21 PM PDT 24 |
Jul 03 07:10:58 PM PDT 24 |
172762100 ps |
| T331 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.90661820 |
|
|
Jul 03 07:10:21 PM PDT 24 |
Jul 03 07:10:56 PM PDT 24 |
29446100 ps |
| T233 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.2145838354 |
|
|
Jul 03 07:09:53 PM PDT 24 |
Jul 03 07:10:20 PM PDT 24 |
38717000 ps |
| T329 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.638610664 |
|
|
Jul 03 07:10:14 PM PDT 24 |
Jul 03 07:10:49 PM PDT 24 |
17554200 ps |
| T236 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.12123423 |
|
|
Jul 03 07:09:54 PM PDT 24 |
Jul 03 07:25:11 PM PDT 24 |
663314200 ps |
| T1122 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1962727881 |
|
|
Jul 03 07:09:37 PM PDT 24 |
Jul 03 07:09:59 PM PDT 24 |
17951400 ps |
| T234 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3569943765 |
|
|
Jul 03 07:10:09 PM PDT 24 |
Jul 03 07:25:43 PM PDT 24 |
343628600 ps |
| T237 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.4218820208 |
|
|
Jul 03 07:09:36 PM PDT 24 |
Jul 03 07:17:29 PM PDT 24 |
706919600 ps |
| T235 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.3305411674 |
|
|
Jul 03 07:09:33 PM PDT 24 |
Jul 03 07:22:28 PM PDT 24 |
1349965200 ps |
| T294 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1113232521 |
|
|
Jul 03 07:09:52 PM PDT 24 |
Jul 03 07:10:17 PM PDT 24 |
195652000 ps |
| T1123 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.628956385 |
|
|
Jul 03 07:10:14 PM PDT 24 |
Jul 03 07:10:48 PM PDT 24 |
49590900 ps |
| T1124 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.1854048118 |
|
|
Jul 03 07:09:53 PM PDT 24 |
Jul 03 07:10:20 PM PDT 24 |
15645200 ps |
| T1125 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.2480561980 |
|
|
Jul 03 07:06:59 PM PDT 24 |
Jul 03 07:07:15 PM PDT 24 |
18218300 ps |
| T1126 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.1870355768 |
|
|
Jul 03 07:09:52 PM PDT 24 |
Jul 03 07:10:17 PM PDT 24 |
31957700 ps |
| T295 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3344962500 |
|
|
Jul 03 07:09:33 PM PDT 24 |
Jul 03 07:10:18 PM PDT 24 |
776543300 ps |
| T1127 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.1513706648 |
|
|
Jul 03 07:09:37 PM PDT 24 |
Jul 03 07:09:58 PM PDT 24 |
22555700 ps |
| T255 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.2798826541 |
|
|
Jul 03 07:10:06 PM PDT 24 |
Jul 03 07:10:39 PM PDT 24 |
35139800 ps |
| T1128 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.2907796521 |
|
|
Jul 03 07:09:36 PM PDT 24 |
Jul 03 07:09:59 PM PDT 24 |
153953100 ps |
| T256 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.556450273 |
|
|
Jul 03 07:09:56 PM PDT 24 |
Jul 03 07:10:27 PM PDT 24 |
105255400 ps |
| T296 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.2070921685 |
|
|
Jul 03 07:09:55 PM PDT 24 |
Jul 03 07:10:42 PM PDT 24 |
858408800 ps |
| T1129 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.1030119554 |
|
|
Jul 03 07:09:53 PM PDT 24 |
Jul 03 07:10:19 PM PDT 24 |
40770900 ps |
| T1130 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.389186427 |
|
|
Jul 03 07:07:03 PM PDT 24 |
Jul 03 07:07:19 PM PDT 24 |
29255100 ps |
| T1131 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.3500875339 |
|
|
Jul 03 07:09:52 PM PDT 24 |
Jul 03 07:10:16 PM PDT 24 |
29631400 ps |
| T257 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2661134533 |
|
|
Jul 03 07:09:35 PM PDT 24 |
Jul 03 07:10:03 PM PDT 24 |
215021100 ps |
| T1132 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1672790785 |
|
|
Jul 03 07:09:35 PM PDT 24 |
Jul 03 07:10:02 PM PDT 24 |
138223700 ps |
| T1133 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.1141433183 |
|
|
Jul 03 07:09:35 PM PDT 24 |
Jul 03 07:09:57 PM PDT 24 |
86274300 ps |
| T1134 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.1898377393 |
|
|
Jul 03 07:09:52 PM PDT 24 |
Jul 03 07:10:16 PM PDT 24 |
12656800 ps |
| T1135 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1620058965 |
|
|
Jul 03 07:09:56 PM PDT 24 |
Jul 03 07:10:24 PM PDT 24 |
162303300 ps |
| T1136 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.1374501747 |
|
|
Jul 03 07:10:12 PM PDT 24 |
Jul 03 07:10:43 PM PDT 24 |
18479600 ps |
| T1137 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.2610352677 |
|
|
Jul 03 07:09:37 PM PDT 24 |
Jul 03 07:10:01 PM PDT 24 |
12923800 ps |
| T238 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1933332283 |
|
|
Jul 03 07:07:14 PM PDT 24 |
Jul 03 07:07:30 PM PDT 24 |
30722100 ps |
| T1138 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.1477664233 |
|
|
Jul 03 07:10:11 PM PDT 24 |
Jul 03 07:10:43 PM PDT 24 |
57023800 ps |
| T266 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.2469159218 |
|
|
Jul 03 07:09:53 PM PDT 24 |
Jul 03 07:10:22 PM PDT 24 |
170291100 ps |
| T1139 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.3368469397 |
|
|
Jul 03 07:09:53 PM PDT 24 |
Jul 03 07:10:16 PM PDT 24 |
11936000 ps |
| T1140 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1343214690 |
|
|
Jul 03 07:07:00 PM PDT 24 |
Jul 03 07:07:14 PM PDT 24 |
63335700 ps |
| T297 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1014532727 |
|
|
Jul 03 07:07:12 PM PDT 24 |
Jul 03 07:07:28 PM PDT 24 |
79955700 ps |
| T1141 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.394087366 |
|
|
Jul 03 07:09:34 PM PDT 24 |
Jul 03 07:09:54 PM PDT 24 |
126298200 ps |
| T1142 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1964838314 |
|
|
Jul 03 07:06:59 PM PDT 24 |
Jul 03 07:07:17 PM PDT 24 |
36457900 ps |
| T1143 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.1378877491 |
|
|
Jul 03 07:09:38 PM PDT 24 |
Jul 03 07:10:01 PM PDT 24 |
45030400 ps |
| T1144 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.411957711 |
|
|
Jul 03 07:09:54 PM PDT 24 |
Jul 03 07:10:19 PM PDT 24 |
24975400 ps |
| T239 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1150723956 |
|
|
Jul 03 07:09:36 PM PDT 24 |
Jul 03 07:09:58 PM PDT 24 |
60470500 ps |
| T1145 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.269464785 |
|
|
Jul 03 07:10:15 PM PDT 24 |
Jul 03 07:10:49 PM PDT 24 |
181180400 ps |
| T258 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.2987931314 |
|
|
Jul 03 07:09:54 PM PDT 24 |
Jul 03 07:10:24 PM PDT 24 |
119744700 ps |
| T1146 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.3400112170 |
|
|
Jul 03 07:09:52 PM PDT 24 |
Jul 03 07:10:16 PM PDT 24 |
127696800 ps |
| T298 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1080451088 |
|
|
Jul 03 07:10:10 PM PDT 24 |
Jul 03 07:11:00 PM PDT 24 |
231072500 ps |
| T1147 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.67226228 |
|
|
Jul 03 07:10:20 PM PDT 24 |
Jul 03 07:10:56 PM PDT 24 |
14618200 ps |
| T1148 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.1129736156 |
|
|
Jul 03 07:09:54 PM PDT 24 |
Jul 03 07:10:19 PM PDT 24 |
15339900 ps |
| T1149 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3304968797 |
|
|
Jul 03 07:09:52 PM PDT 24 |
Jul 03 07:10:17 PM PDT 24 |
42297100 ps |
| T1150 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.805207583 |
|
|
Jul 03 07:10:16 PM PDT 24 |
Jul 03 07:10:49 PM PDT 24 |
18502800 ps |
| T264 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1891653829 |
|
|
Jul 03 07:10:09 PM PDT 24 |
Jul 03 07:25:34 PM PDT 24 |
344295300 ps |
| T1151 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.772487397 |
|
|
Jul 03 07:07:13 PM PDT 24 |
Jul 03 07:07:31 PM PDT 24 |
40104100 ps |
| T259 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2899550087 |
|
|
Jul 03 07:09:36 PM PDT 24 |
Jul 03 07:10:04 PM PDT 24 |
640897500 ps |
| T299 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3110098964 |
|
|
Jul 03 07:07:03 PM PDT 24 |
Jul 03 07:07:22 PM PDT 24 |
107272500 ps |
| T300 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1364231779 |
|
|
Jul 03 07:07:01 PM PDT 24 |
Jul 03 07:07:34 PM PDT 24 |
33005600 ps |
| T1152 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2118552031 |
|
|
Jul 03 07:09:34 PM PDT 24 |
Jul 03 07:10:14 PM PDT 24 |
158651100 ps |
| T267 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1996413180 |
|
|
Jul 03 07:10:08 PM PDT 24 |
Jul 03 07:10:42 PM PDT 24 |
61059500 ps |
| T1153 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.1576115986 |
|
|
Jul 03 07:09:55 PM PDT 24 |
Jul 03 07:10:25 PM PDT 24 |
47012500 ps |
| T1154 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3892525411 |
|
|
Jul 03 07:07:12 PM PDT 24 |
Jul 03 07:07:45 PM PDT 24 |
18634500 ps |
| T1155 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.2102301071 |
|
|
Jul 03 07:06:58 PM PDT 24 |
Jul 03 07:07:14 PM PDT 24 |
14098100 ps |
| T269 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.685437339 |
|
|
Jul 03 07:09:53 PM PDT 24 |
Jul 03 07:10:20 PM PDT 24 |
230946100 ps |
| T1156 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2946479343 |
|
|
Jul 03 07:06:59 PM PDT 24 |
Jul 03 07:07:17 PM PDT 24 |
22456600 ps |
| T1157 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2132378007 |
|
|
Jul 03 07:09:53 PM PDT 24 |
Jul 03 07:10:19 PM PDT 24 |
81299000 ps |
| T301 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.2481957 |
|
|
Jul 03 07:09:54 PM PDT 24 |
Jul 03 07:10:41 PM PDT 24 |
249541000 ps |
| T1158 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.345893156 |
|
|
Jul 03 07:10:10 PM PDT 24 |
Jul 03 07:10:46 PM PDT 24 |
105690300 ps |
| T1159 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.1672307502 |
|
|
Jul 03 07:07:14 PM PDT 24 |
Jul 03 07:08:22 PM PDT 24 |
1332360800 ps |
| T350 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.4208335260 |
|
|
Jul 03 07:09:34 PM PDT 24 |
Jul 03 07:16:06 PM PDT 24 |
759183600 ps |
| T1160 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.3199166789 |
|
|
Jul 03 07:10:05 PM PDT 24 |
Jul 03 07:10:32 PM PDT 24 |
11163500 ps |
| T1161 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.1715074289 |
|
|
Jul 03 07:09:54 PM PDT 24 |
Jul 03 07:10:21 PM PDT 24 |
43484400 ps |
| T1162 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.992170054 |
|
|
Jul 03 07:09:52 PM PDT 24 |
Jul 03 07:10:14 PM PDT 24 |
23225400 ps |
| T268 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3814103347 |
|
|
Jul 03 07:07:05 PM PDT 24 |
Jul 03 07:07:22 PM PDT 24 |
42835400 ps |
| T348 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.2612847782 |
|
|
Jul 03 07:07:09 PM PDT 24 |
Jul 03 07:22:19 PM PDT 24 |
705010700 ps |
| T1163 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.755443478 |
|
|
Jul 03 07:10:09 PM PDT 24 |
Jul 03 07:10:40 PM PDT 24 |
15782200 ps |
| T1164 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.74349820 |
|
|
Jul 03 07:06:58 PM PDT 24 |
Jul 03 07:08:11 PM PDT 24 |
2432204800 ps |
| T1165 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.476808394 |
|
|
Jul 03 07:09:33 PM PDT 24 |
Jul 03 07:09:55 PM PDT 24 |
148044900 ps |
| T1166 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.3591701156 |
|
|
Jul 03 07:10:11 PM PDT 24 |
Jul 03 07:10:45 PM PDT 24 |
14483800 ps |
| T1167 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.2638120566 |
|
|
Jul 03 07:10:14 PM PDT 24 |
Jul 03 07:10:47 PM PDT 24 |
148444600 ps |
| T1168 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.3400009149 |
|
|
Jul 03 07:09:53 PM PDT 24 |
Jul 03 07:10:21 PM PDT 24 |
28845400 ps |
| T1169 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2281240937 |
|
|
Jul 03 07:10:08 PM PDT 24 |
Jul 03 07:10:39 PM PDT 24 |
12039100 ps |
| T1170 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.3881960848 |
|
|
Jul 03 07:09:53 PM PDT 24 |
Jul 03 07:10:19 PM PDT 24 |
30054600 ps |
| T1171 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.1156774735 |
|
|
Jul 03 07:10:08 PM PDT 24 |
Jul 03 07:10:36 PM PDT 24 |
57520600 ps |
| T1172 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3372713245 |
|
|
Jul 03 07:09:35 PM PDT 24 |
Jul 03 07:10:25 PM PDT 24 |
1108703000 ps |
| T265 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3235060741 |
|
|
Jul 03 07:09:53 PM PDT 24 |
Jul 03 07:22:45 PM PDT 24 |
3285023600 ps |
| T1173 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1976013352 |
|
|
Jul 03 07:10:08 PM PDT 24 |
Jul 03 07:10:41 PM PDT 24 |
95398400 ps |
| T1174 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2716940953 |
|
|
Jul 03 07:09:54 PM PDT 24 |
Jul 03 07:10:23 PM PDT 24 |
313587500 ps |
| T263 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3112838210 |
|
|
Jul 03 07:07:08 PM PDT 24 |
Jul 03 07:07:28 PM PDT 24 |
168801400 ps |
| T1175 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.3370264555 |
|
|
Jul 03 07:09:52 PM PDT 24 |
Jul 03 07:10:16 PM PDT 24 |
138275100 ps |
| T1176 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.3879286190 |
|
|
Jul 03 07:09:54 PM PDT 24 |
Jul 03 07:10:18 PM PDT 24 |
58569300 ps |
| T1177 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3459739720 |
|
|
Jul 03 07:10:11 PM PDT 24 |
Jul 03 07:10:45 PM PDT 24 |
14932900 ps |
| T1178 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.4219046999 |
|
|
Jul 03 07:10:05 PM PDT 24 |
Jul 03 07:10:35 PM PDT 24 |
508399200 ps |
| T271 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.246268747 |
|
|
Jul 03 07:07:00 PM PDT 24 |
Jul 03 07:07:21 PM PDT 24 |
116043000 ps |
| T1179 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.2494411641 |
|
|
Jul 03 07:07:10 PM PDT 24 |
Jul 03 07:07:27 PM PDT 24 |
12965200 ps |
| T1180 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3996551479 |
|
|
Jul 03 07:10:08 PM PDT 24 |
Jul 03 07:10:37 PM PDT 24 |
176641500 ps |
| T1181 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1990764571 |
|
|
Jul 03 07:10:11 PM PDT 24 |
Jul 03 07:10:43 PM PDT 24 |
11656300 ps |
| T1182 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.803752693 |
|
|
Jul 03 07:09:38 PM PDT 24 |
Jul 03 07:10:00 PM PDT 24 |
61515200 ps |
| T1183 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.573873347 |
|
|
Jul 03 07:09:53 PM PDT 24 |
Jul 03 07:10:17 PM PDT 24 |
60443800 ps |
| T1184 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.3974665864 |
|
|
Jul 03 07:09:52 PM PDT 24 |
Jul 03 07:10:16 PM PDT 24 |
38381900 ps |
| T1185 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.882443181 |
|
|
Jul 03 07:09:50 PM PDT 24 |
Jul 03 07:10:11 PM PDT 24 |
18838700 ps |
| T1186 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.4232333661 |
|
|
Jul 03 07:07:14 PM PDT 24 |
Jul 03 07:07:32 PM PDT 24 |
41355800 ps |
| T1187 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.2915498581 |
|
|
Jul 03 07:10:13 PM PDT 24 |
Jul 03 07:10:47 PM PDT 24 |
34499800 ps |
| T1188 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.494789208 |
|
|
Jul 03 07:09:56 PM PDT 24 |
Jul 03 07:10:22 PM PDT 24 |
19143100 ps |
| T1189 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.2944200087 |
|
|
Jul 03 07:10:12 PM PDT 24 |
Jul 03 07:10:43 PM PDT 24 |
27639000 ps |
| T1190 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.1149399070 |
|
|
Jul 03 07:10:15 PM PDT 24 |
Jul 03 07:10:49 PM PDT 24 |
16693500 ps |
| T349 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.2983320542 |
|
|
Jul 03 07:07:03 PM PDT 24 |
Jul 03 07:22:15 PM PDT 24 |
809872300 ps |
| T1191 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.1411957515 |
|
|
Jul 03 07:10:11 PM PDT 24 |
Jul 03 07:10:43 PM PDT 24 |
15300900 ps |
| T1192 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.4242150221 |
|
|
Jul 03 07:10:08 PM PDT 24 |
Jul 03 07:10:37 PM PDT 24 |
23052300 ps |
| T270 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.232034505 |
|
|
Jul 03 07:09:51 PM PDT 24 |
Jul 03 07:16:27 PM PDT 24 |
1805870000 ps |
| T1193 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2074328243 |
|
|
Jul 03 07:09:52 PM PDT 24 |
Jul 03 07:10:16 PM PDT 24 |
40051300 ps |
| T1194 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.1950656553 |
|
|
Jul 03 07:09:34 PM PDT 24 |
Jul 03 07:10:00 PM PDT 24 |
112771000 ps |
| T1195 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1610673150 |
|
|
Jul 03 07:10:06 PM PDT 24 |
Jul 03 07:10:37 PM PDT 24 |
296251900 ps |
| T1196 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3266159133 |
|
|
Jul 03 07:09:52 PM PDT 24 |
Jul 03 07:10:16 PM PDT 24 |
126758500 ps |
| T1197 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3696884602 |
|
|
Jul 03 07:09:51 PM PDT 24 |
Jul 03 07:10:13 PM PDT 24 |
54310400 ps |
| T1198 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.620604911 |
|
|
Jul 03 07:09:56 PM PDT 24 |
Jul 03 07:10:28 PM PDT 24 |
521074600 ps |
| T1199 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.966607722 |
|
|
Jul 03 07:10:13 PM PDT 24 |
Jul 03 07:10:47 PM PDT 24 |
55544500 ps |
| T1200 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1135786700 |
|
|
Jul 03 07:07:10 PM PDT 24 |
Jul 03 07:07:52 PM PDT 24 |
2501713400 ps |
| T1201 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.3352744529 |
|
|
Jul 03 07:09:52 PM PDT 24 |
Jul 03 07:10:13 PM PDT 24 |
13555200 ps |
| T351 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.1742979079 |
|
|
Jul 03 07:09:55 PM PDT 24 |
Jul 03 07:25:21 PM PDT 24 |
903666100 ps |
| T1202 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.2916221186 |
|
|
Jul 03 07:10:15 PM PDT 24 |
Jul 03 07:10:48 PM PDT 24 |
24641700 ps |
| T1203 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.879557871 |
|
|
Jul 03 07:09:53 PM PDT 24 |
Jul 03 07:10:20 PM PDT 24 |
156575300 ps |
| T1204 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.3594452294 |
|
|
Jul 03 07:09:33 PM PDT 24 |
Jul 03 07:09:50 PM PDT 24 |
20888800 ps |
| T1205 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1733367557 |
|
|
Jul 03 07:09:55 PM PDT 24 |
Jul 03 07:10:22 PM PDT 24 |
30924000 ps |
| T240 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2760931653 |
|
|
Jul 03 07:07:00 PM PDT 24 |
Jul 03 07:07:16 PM PDT 24 |
49054000 ps |
| T1206 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.349661620 |
|
|
Jul 03 07:07:11 PM PDT 24 |
Jul 03 07:07:28 PM PDT 24 |
48101600 ps |
| T1207 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.709148218 |
|
|
Jul 03 07:06:59 PM PDT 24 |
Jul 03 07:07:19 PM PDT 24 |
317161100 ps |
| T1208 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.102599848 |
|
|
Jul 03 07:09:34 PM PDT 24 |
Jul 03 07:10:15 PM PDT 24 |
661798500 ps |
| T1209 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1012921026 |
|
|
Jul 03 07:09:37 PM PDT 24 |
Jul 03 07:10:00 PM PDT 24 |
39798000 ps |
| T1210 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.3918816739 |
|
|
Jul 03 07:09:34 PM PDT 24 |
Jul 03 07:09:57 PM PDT 24 |
35649200 ps |
| T1211 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.3028872000 |
|
|
Jul 03 07:09:56 PM PDT 24 |
Jul 03 07:10:26 PM PDT 24 |
260247100 ps |
| T1212 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.4117978506 |
|
|
Jul 03 07:10:04 PM PDT 24 |
Jul 03 07:10:37 PM PDT 24 |
873325000 ps |
| T1213 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.4290429198 |
|
|
Jul 03 07:07:06 PM PDT 24 |
Jul 03 07:07:24 PM PDT 24 |
125643100 ps |
| T1214 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.2463291512 |
|
|
Jul 03 07:09:54 PM PDT 24 |
Jul 03 07:10:23 PM PDT 24 |
104738100 ps |
| T1215 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.70680683 |
|
|
Jul 03 07:09:35 PM PDT 24 |
Jul 03 07:10:01 PM PDT 24 |
43266700 ps |
| T1216 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1670225772 |
|
|
Jul 03 07:09:56 PM PDT 24 |
Jul 03 07:10:26 PM PDT 24 |
306186800 ps |
| T1217 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.4070297941 |
|
|
Jul 03 07:10:10 PM PDT 24 |
Jul 03 07:10:41 PM PDT 24 |
57702000 ps |
| T353 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2418072927 |
|
|
Jul 03 07:09:36 PM PDT 24 |
Jul 03 07:24:47 PM PDT 24 |
2093425000 ps |
| T1218 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.1961978083 |
|
|
Jul 03 07:10:14 PM PDT 24 |
Jul 03 07:10:47 PM PDT 24 |
23602900 ps |
| T1219 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.266437292 |
|
|
Jul 03 07:09:51 PM PDT 24 |
Jul 03 07:10:15 PM PDT 24 |
14280000 ps |
| T1220 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2962232558 |
|
|
Jul 03 07:07:11 PM PDT 24 |
Jul 03 07:07:38 PM PDT 24 |
97910900 ps |
| T1221 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.4103981110 |
|
|
Jul 03 07:09:53 PM PDT 24 |
Jul 03 07:10:17 PM PDT 24 |
18254300 ps |
| T1222 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3241538998 |
|
|
Jul 03 07:10:11 PM PDT 24 |
Jul 03 07:10:43 PM PDT 24 |
36034900 ps |
| T1223 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.590098680 |
|
|
Jul 03 07:09:50 PM PDT 24 |
Jul 03 07:10:09 PM PDT 24 |
28109800 ps |
| T241 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.890508681 |
|
|
Jul 03 07:07:03 PM PDT 24 |
Jul 03 07:07:18 PM PDT 24 |
44103700 ps |
| T1224 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.2492085604 |
|
|
Jul 03 07:09:36 PM PDT 24 |
Jul 03 07:10:01 PM PDT 24 |
90173500 ps |
| T1225 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.1155945190 |
|
|
Jul 03 07:09:34 PM PDT 24 |
Jul 03 07:09:55 PM PDT 24 |
24831000 ps |
| T1226 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.2730142122 |
|
|
Jul 03 07:09:54 PM PDT 24 |
Jul 03 07:10:18 PM PDT 24 |
85297600 ps |
| T1227 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.625094363 |
|
|
Jul 03 07:09:37 PM PDT 24 |
Jul 03 07:10:19 PM PDT 24 |
307781200 ps |
| T1228 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.4254998653 |
|
|
Jul 03 07:07:13 PM PDT 24 |
Jul 03 07:07:30 PM PDT 24 |
87947400 ps |
| T1229 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.688653167 |
|
|
Jul 03 07:09:53 PM PDT 24 |
Jul 03 07:10:19 PM PDT 24 |
84346800 ps |
| T1230 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.2737251313 |
|
|
Jul 03 07:10:14 PM PDT 24 |
Jul 03 07:10:48 PM PDT 24 |
16293600 ps |
| T1231 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.274033202 |
|
|
Jul 03 07:10:07 PM PDT 24 |
Jul 03 07:10:40 PM PDT 24 |
89916100 ps |
| T1232 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.330326663 |
|
|
Jul 03 07:09:53 PM PDT 24 |
Jul 03 07:17:53 PM PDT 24 |
379382000 ps |
| T1233 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1063147979 |
|
|
Jul 03 07:10:07 PM PDT 24 |
Jul 03 07:10:38 PM PDT 24 |
41675500 ps |
| T1234 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.896895883 |
|
|
Jul 03 07:07:04 PM PDT 24 |
Jul 03 07:07:19 PM PDT 24 |
31993000 ps |
| T1235 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.1224064549 |
|
|
Jul 03 07:09:51 PM PDT 24 |
Jul 03 07:10:14 PM PDT 24 |
305820800 ps |
| T1236 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.3481840527 |
|
|
Jul 03 07:09:37 PM PDT 24 |
Jul 03 07:10:05 PM PDT 24 |
193633200 ps |
| T1237 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.2303564542 |
|
|
Jul 03 07:09:56 PM PDT 24 |
Jul 03 07:25:19 PM PDT 24 |
705638900 ps |
| T1238 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.3987194069 |
|
|
Jul 03 07:09:35 PM PDT 24 |
Jul 03 07:10:05 PM PDT 24 |
60311100 ps |
| T1239 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.3525365535 |
|
|
Jul 03 07:10:20 PM PDT 24 |
Jul 03 07:10:56 PM PDT 24 |
31188000 ps |
| T1240 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.647294405 |
|
|
Jul 03 07:07:10 PM PDT 24 |
Jul 03 07:07:31 PM PDT 24 |
113754500 ps |
| T1241 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.437461375 |
|
|
Jul 03 07:09:53 PM PDT 24 |
Jul 03 07:10:22 PM PDT 24 |
95719700 ps |
| T1242 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.716592605 |
|
|
Jul 03 07:07:00 PM PDT 24 |
Jul 03 07:14:46 PM PDT 24 |
435955800 ps |
| T1243 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1262140932 |
|
|
Jul 03 07:09:37 PM PDT 24 |
Jul 03 07:10:01 PM PDT 24 |
24960900 ps |
| T1244 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.3456910558 |
|
|
Jul 03 07:10:15 PM PDT 24 |
Jul 03 07:10:49 PM PDT 24 |
25863100 ps |
| T1245 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.2535013943 |
|
|
Jul 03 07:09:53 PM PDT 24 |
Jul 03 07:10:18 PM PDT 24 |
58752400 ps |
| T1246 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1023550005 |
|
|
Jul 03 07:09:53 PM PDT 24 |
Jul 03 07:10:21 PM PDT 24 |
139843700 ps |
| T1247 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.308842593 |
|
|
Jul 03 07:09:51 PM PDT 24 |
Jul 03 07:10:16 PM PDT 24 |
90810600 ps |
| T347 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.2104891753 |
|
|
Jul 03 07:09:53 PM PDT 24 |
Jul 03 07:10:19 PM PDT 24 |
116559500 ps |
| T1248 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.2445456297 |
|
|
Jul 03 07:09:51 PM PDT 24 |
Jul 03 07:10:12 PM PDT 24 |
29480100 ps |
| T242 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.4024637041 |
|
|
Jul 03 07:09:34 PM PDT 24 |
Jul 03 07:09:54 PM PDT 24 |
30204000 ps |
| T1249 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3980861472 |
|
|
Jul 03 07:09:55 PM PDT 24 |
Jul 03 07:17:57 PM PDT 24 |
610248600 ps |
| T1250 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.4290344234 |
|
|
Jul 03 07:09:36 PM PDT 24 |
Jul 03 07:10:02 PM PDT 24 |
620576100 ps |
| T1251 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.3416735013 |
|
|
Jul 03 07:10:09 PM PDT 24 |
Jul 03 07:10:38 PM PDT 24 |
50038900 ps |