Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	288834	1		T1	2		T2	1		T3	1
all_values[1]	288834	1		T1	2		T2	1		T3	1
all_values[2]	288834	1		T1	2		T2	1		T3	1
all_values[3]	288834	1		T1	2		T2	1		T3	1
all_values[4]	288834	1		T1	2		T2	1		T3	1
all_values[5]	288834	1		T1	2		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	583724	1		T1	12		T2	6		T3	6
auto[1]	1149280	1		T25	26784		T37	5628		T38	22556

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	852222	1		T1	7		T2	4		T3	4
auto[1]	880782	1		T1	5		T2	2		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	288651	1		T1	2		T2	1		T3	1
all_values[0]	auto[1]	auto[1]	183	1		T285	1		T286	3		T339	4
all_values[1]	auto[0]	auto[1]	288677	1		T1	2		T2	1		T3	1
all_values[1]	auto[1]	auto[1]	157	1		T285	2		T286	3		T339	3
all_values[2]	auto[0]	auto[0]	1531	1		T1	2		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	57	1		T286	1		T339	1		T342	1
all_values[2]	auto[1]	auto[0]	287177	1		T25	6696		T37	1407		T38	5639
all_values[2]	auto[1]	auto[1]	69	1		T285	2		T286	2		T339	1
all_values[3]	auto[0]	auto[0]	1541	1		T1	2		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	66	1		T285	1		T339	2		T340	1
all_values[3]	auto[1]	auto[0]	76713	1		T37	48		T38	25		T27	1567
all_values[3]	auto[1]	auto[1]	210514	1		T25	6696		T37	1359		T38	5614
all_values[4]	auto[0]	auto[0]	1107	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	492	1		T1	1		T4	1		T17	1
all_values[4]	auto[1]	auto[0]	195486	1		T25	5022		T37	1057		T38	5227
all_values[4]	auto[1]	auto[1]	91749	1		T25	1674		T37	350		T38	412
all_values[5]	auto[0]	auto[0]	1499	1		T1	2		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	103	1		T39	1		T40	1		T41	1
all_values[5]	auto[1]	auto[0]	287168	1		T25	6696		T37	1407		T38	5639
all_values[5]	auto[1]	auto[1]	64	1		T285	4		T286	3		T339	4