Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	240125	1		T1	2		T4	9		T17	2
auto[FlashEraseBank]	272533	1		T4	7		T5	1		T6	11

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	249670	1		T1	2		T4	8		T6	26
auto[FlashOpProgram]	244372	1		T4	4		T5	1		T7	3
auto[FlashOpErase]	14616	1		T4	4		T17	2		T5	2
auto[FlashOpInvalid]	4000	1		T217	200		T140	200		T141	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	249670	1		T1	2		T4	8		T6	26
op[FlashOpProgram]	244372	1		T4	4		T5	1		T7	3
op[FlashOpErase]	14616	1		T4	4		T17	2		T5	2
read_erase_read	589	1		T4	2		T6	12		T30	1
read_prog_read	872	1		T4	1		T23	1		T36	10

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	375878	1		T1	1		T4	16		T17	2
auto[FlashPartInfo]	133063	1		T1	1		T6	22		T60	204
auto[FlashPartInfo1]	792	1		T9	3		T123	64		T33	24
auto[FlashPartInfo2]	2925	1		T60	1		T9	14		T37	84

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	180045	1		T1	1		T4	8		T6	10
auto[FlashPartData]	auto[FlashOpProgram]	188232	1		T4	4		T5	1		T7	3
auto[FlashPartData]	auto[FlashOpErase]	3677	1		T4	4		T17	2		T5	2
auto[FlashPartData]	auto[FlashOpInvalid]	3924	1		T217	196		T140	196		T141	192
auto[FlashPartInfo]	auto[FlashOpRead]	67043	1		T1	1		T6	16		T9	213
auto[FlashPartInfo]	auto[FlashOpProgram]	55047	1		T60	204		T10	3		T23	1
auto[FlashPartInfo]	auto[FlashOpErase]	10911	1		T6	6		T30	14		T31	8
auto[FlashPartInfo]	auto[FlashOpInvalid]	62	1		T217	4		T140	4		T141	8
auto[FlashPartInfo1]	auto[FlashOpRead]	622	1		T9	3		T123	32		T33	24
auto[FlashPartInfo1]	auto[FlashOpProgram]	163	1		T123	32		T138	32		T124	1
auto[FlashPartInfo1]	auto[FlashOpErase]	3	1		T124	1		T125	1		T145	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T124	2		T145	2		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1960	1		T9	14		T37	84		T38	69
auto[FlashPartInfo2]	auto[FlashOpProgram]	930	1		T60	1		T122	6		T123	64
auto[FlashPartInfo2]	auto[FlashOpErase]	25	1		T226	1		T136	1		T310	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	10	1		T157	2		T410	2		T411	2