Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	28431	1		T4	32		T5	4		T7	1
auto[1]	44	1		T221	1		T310	14		T412	1
auto[2]	36	1		T310	4		T413	1		T144	4
auto[3]	223	1		T6	12		T23	1		T24	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7190	1		T4	8		T5	1		T6	4
evic_idx[1]	7187	1		T4	8		T5	1		T6	2
evic_idx[2]	7178	1		T4	8		T5	1		T6	2
evic_idx[3]	7179	1		T4	8		T5	1		T6	4

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	27818	1		T4	8		T6	12		T85	348
evic_op[2]	326	1		T4	16		T7	1		T23	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	6897	1		T4	2		T85	87		T86	151
evic_idx[0]	evic_op[1]	auto[1]	10	1		T310	4		T414	2		T415	4
evic_idx[0]	evic_op[1]	auto[2]	4	1		T310	1		T416	1		T417	1
evic_idx[0]	evic_op[1]	auto[3]	50	1		T6	4		T143	1		T226	1
evic_idx[0]	evic_op[2]	auto[0]	69	1		T4	4		T274	8		T368	1
evic_idx[0]	evic_op[2]	auto[1]	1	1		T418	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[2]	3	1		T412	1		T419	1		T420	1
evic_idx[0]	evic_op[2]	auto[3]	8	1		T26	1		T251	1		T229	1
evic_idx[1]	evic_op[1]	auto[0]	6897	1		T4	2		T85	87		T86	151
evic_idx[1]	evic_op[1]	auto[1]	10	1		T310	4		T414	2		T415	4
evic_idx[1]	evic_op[1]	auto[2]	2	1		T310	1		T417	1		-	-
evic_idx[1]	evic_op[1]	auto[3]	44	1		T6	2		T310	3		T228	3
evic_idx[1]	evic_op[2]	auto[0]	71	1		T4	4		T227	1		T274	8
evic_idx[1]	evic_op[2]	auto[1]	3	1		T221	1		T412	1		T421	1
evic_idx[1]	evic_op[2]	auto[2]	1	1		T419	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[3]	11	1		T381	1		T302	1		T422	1
evic_idx[2]	evic_op[1]	auto[0]	6895	1		T4	2		T85	87		T86	151
evic_idx[2]	evic_op[1]	auto[1]	9	1		T310	4		T414	2		T415	3
evic_idx[2]	evic_op[1]	auto[2]	2	1		T310	1		T417	1		-	-
evic_idx[2]	evic_op[1]	auto[3]	44	1		T6	2		T310	3		T228	5
evic_idx[2]	evic_op[2]	auto[0]	68	1		T4	4		T42	1		T274	8
evic_idx[2]	evic_op[2]	auto[1]	1	1		T423	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[2]	1	1		T424	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[3]	11	1		T23	1		T24	1		T222	1
evic_idx[3]	evic_op[1]	auto[0]	6894	1		T4	2		T85	87		T86	151
evic_idx[3]	evic_op[1]	auto[1]	7	1		T310	2		T414	2		T415	3
evic_idx[3]	evic_op[1]	auto[2]	3	1		T310	1		T417	2		-	-
evic_idx[3]	evic_op[1]	auto[3]	50	1		T6	4		T143	1		T226	1
evic_idx[3]	evic_op[2]	auto[0]	66	1		T4	4		T7	1		T274	8
evic_idx[3]	evic_op[2]	auto[1]	3	1		T425	1		T77	1		T418	1
evic_idx[3]	evic_op[2]	auto[2]	4	1		T413	1		T419	3		-	-
evic_idx[3]	evic_op[2]	auto[3]	5	1		T426	1		T427	1		T428	1