Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg
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Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv



Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 5 0 5 100.00
Crosses 6 0 6 100.00


Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
instr_type_cp 3 0 3 100.00 100 1 1 0
key_cp 2 0 2 100.00 100 1 1 2


Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
key_instr_cross 6 0 6 100.00 100 1 1 0


Summary for Variable instr_type_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for instr_type_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
others 4906 1 T47 131 T48 123 T49 184
instr_types[0] 5996 1 T47 292 T48 205 T49 319
instr_types[1] 4272407 1 T4 93 T5 53 T6 24



Summary for Variable key_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4281178 1 T4 93 T5 53 T6 24
auto[1] 2131 1 T47 247 T48 176 T49 256



Summary for Cross key_instr_cross

Samples crossed: key_cp instr_type_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 6 0 6 100.00


Automatically Generated Cross Bins for key_instr_cross

Bins
key_cpinstr_type_cpCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] others 4411 1 T47 83 T48 58 T49 113
auto[0] instr_types[0] 5199 1 T47 180 T48 158 T49 220
auto[0] instr_types[1] 4271568 1 T4 93 T5 53 T6 24
auto[1] others 495 1 T47 48 T48 65 T49 71
auto[1] instr_types[0] 797 1 T47 112 T48 47 T49 99
auto[1] instr_types[1] 839 1 T47 87 T48 64 T49 86

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%