Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

---

Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	33061	1		T38	2396		T230	1079		T236	13706
rd_lvl[2]	24670	1		T38	1010		T230	204		T236	9718
rd_lvl[3]	12733	1		T38	371		T345	1418		T346	891
rd_lvl[4]	21625	1		T25	5514		T37	1013		T38	255
rd_lvl[5]	12094	1		T25	1182		T37	242		T38	70
rd_lvl[6]	8794	1		T38	4		T150	1335		T261	2538
rd_lvl[7]	11996	1		T37	22		T38	51		T150	45
rd_lvl[8]	11256	1		T37	2		T38	47		T303	1422
rd_lvl[9]	7314	1		T38	58		T230	1		T347	3
rd_lvl[10]	11134	1		T38	39		T347	2		T348	1345
rd_lvl[11]	4949	1		T38	94		T33	60		T34	384
rd_lvl[12]	5049	1		T37	19		T38	3		T33	29
rd_lvl[13]	2697	1		T38	1		T349	607		T346	87
rd_lvl[14]	8051	1		T38	93		T33	1		T235	1258
rd_lvl[15]	2592	1		T235	351		T35	480		T350	303