Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	288834	1		T1	2		T2	1		T3	1
all_pins[1]	288834	1		T1	2		T2	1		T3	1
all_pins[2]	288834	1		T1	2		T2	1		T3	1
all_pins[3]	288834	1		T1	2		T2	1		T3	1
all_pins[4]	288834	1		T1	2		T2	1		T3	1
all_pins[5]	288834	1		T1	2		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1450548	1		T1	12		T2	6		T3	6
values[0x1]	282456	1		T25	8370		T37	1651		T38	4942
transitions[0x0=>0x1]	258115	1		T25	6696		T37	1346		T38	4517
transitions[0x1=>0x0]	258096	1		T25	6696		T37	1346		T38	4517

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	288651	1		T1	2		T2	1		T3	1
all_pins[0]	values[0x1]	183	1		T285	1		T286	3		T339	4
all_pins[0]	transitions[0x0=>0x1]	85	1		T286	1		T339	1		T340	3
all_pins[0]	transitions[0x1=>0x0]	59	1		T285	1		T286	1		T341	1
all_pins[1]	values[0x0]	288677	1		T1	2		T2	1		T3	1
all_pins[1]	values[0x1]	157	1		T285	2		T286	3		T339	3
all_pins[1]	transitions[0x0=>0x1]	122	1		T285	1		T286	2		T339	2
all_pins[1]	transitions[0x1=>0x0]	2837	1		T35	1072		T350	256		T352	1
all_pins[2]	values[0x0]	285962	1		T1	2		T2	1		T3	1
all_pins[2]	values[0x1]	2872	1		T35	1072		T350	256		T352	1
all_pins[2]	transitions[0x0=>0x1]	48	1		T285	1		T286	1		T339	1
all_pins[2]	transitions[0x1=>0x0]	178097	1		T25	6696		T37	1298		T38	4492
all_pins[3]	values[0x0]	107913	1		T1	2		T2	1		T3	1
all_pins[3]	values[0x1]	180921	1		T25	6696		T37	1298		T38	4492
all_pins[3]	transitions[0x0=>0x1]	159601	1		T25	5022		T37	993		T38	4067
all_pins[3]	transitions[0x1=>0x0]	76939	1		T37	48		T38	25		T27	1566
all_pins[4]	values[0x0]	190575	1		T1	2		T2	1		T3	1
all_pins[4]	values[0x1]	98259	1		T25	1674		T37	353		T38	450
all_pins[4]	transitions[0x0=>0x1]	98236	1		T25	1674		T37	353		T38	450
all_pins[4]	transitions[0x1=>0x0]	41	1		T286	1		T339	4		T342	1
all_pins[5]	values[0x0]	288770	1		T1	2		T2	1		T3	1
all_pins[5]	values[0x1]	64	1		T285	4		T286	3		T339	4
all_pins[5]	transitions[0x0=>0x1]	23	1		T285	2		T286	1		T339	1
all_pins[5]	transitions[0x1=>0x0]	123	1		T286	2		T339	2		T340	1