Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	284	1		T285	4		T286	7		T339	7
all_values[1]	284	1		T285	4		T286	7		T339	7
all_values[2]	284	1		T285	4		T286	7		T339	7
all_values[3]	284	1		T285	4		T286	7		T339	7
all_values[4]	284	1		T285	4		T286	7		T339	7
all_values[5]	284	1		T285	4		T286	7		T339	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	883	1		T285	5		T286	19		T339	21
auto[1]	821	1		T285	19		T286	23		T339	21

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	532	1		T285	4		T286	13		T339	17
auto[1]	1172	1		T285	20		T286	29		T339	25

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	977	1		T285	13		T286	23		T339	28
auto[1]	727	1		T285	11		T286	19		T339	14

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	78	1		T285	1		T286	3		T339	1
all_values[0]	auto[0]	auto[1]	auto[1]	91	1		T285	2		T339	3		T340	1
all_values[0]	auto[1]	auto[0]	auto[1]	55	1		T285	1		T286	1		T341	1
all_values[0]	auto[1]	auto[1]	auto[1]	60	1		T286	3		T339	3		T341	2
all_values[1]	auto[0]	auto[0]	auto[1]	88	1		T285	1		T286	2		T339	2
all_values[1]	auto[0]	auto[1]	auto[1]	77	1		T285	2		T286	2		T339	3
all_values[1]	auto[1]	auto[0]	auto[1]	68	1		T286	1		T339	1		T340	3
all_values[1]	auto[1]	auto[1]	auto[1]	51	1		T285	1		T286	2		T339	1
all_values[2]	auto[0]	auto[0]	auto[0]	74	1		T286	3		T339	2		T340	2
all_values[2]	auto[0]	auto[1]	auto[0]	84	1		T285	2		T286	1		T339	3
all_values[2]	auto[1]	auto[0]	auto[1]	70	1		T286	1		T339	2		T341	1
all_values[2]	auto[1]	auto[1]	auto[1]	56	1		T285	2		T286	2		T341	3
all_values[3]	auto[0]	auto[0]	auto[0]	87	1		T285	2		T286	3		T339	3
all_values[3]	auto[0]	auto[1]	auto[0]	63	1		T286	2		T339	1		T340	1
all_values[3]	auto[1]	auto[0]	auto[1]	69	1		T339	1		T340	1		T341	2
all_values[3]	auto[1]	auto[1]	auto[1]	65	1		T285	2		T286	2		T339	2
all_values[4]	auto[0]	auto[0]	auto[0]	59	1		T286	1		T339	5		T342	3
all_values[4]	auto[0]	auto[0]	auto[1]	31	1		T340	1		T341	1		T343	2
all_values[4]	auto[0]	auto[1]	auto[0]	50	1		T286	3		T339	2		T341	4
all_values[4]	auto[0]	auto[1]	auto[1]	30	1		T285	2		T340	1		T342	1
all_values[4]	auto[1]	auto[0]	auto[1]	59	1		T340	1		T341	2		T342	1
all_values[4]	auto[1]	auto[1]	auto[1]	55	1		T285	2		T286	3		T340	1
all_values[5]	auto[0]	auto[0]	auto[0]	50	1		T339	1		T341	1		T344	1
all_values[5]	auto[0]	auto[0]	auto[1]	33	1		T286	3		T339	1		T341	1
all_values[5]	auto[0]	auto[1]	auto[0]	65	1		T340	1		T341	4		T342	2
all_values[5]	auto[0]	auto[1]	auto[1]	17	1		T285	1		T339	1		T340	1
all_values[5]	auto[1]	auto[0]	auto[1]	62	1		T286	1		T339	2		T340	1
all_values[5]	auto[1]	auto[1]	auto[1]	57	1		T285	3		T286	3		T339	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal