| T1073 |
/workspace/coverage/default/23.flash_ctrl_otp_reset.705055696 |
|
|
Jul 04 05:49:59 PM PDT 24 |
Jul 04 05:51:50 PM PDT 24 |
178074100 ps |
| T1074 |
/workspace/coverage/default/2.flash_ctrl_ro_derr.973387576 |
|
|
Jul 04 05:45:02 PM PDT 24 |
Jul 04 05:47:17 PM PDT 24 |
575839400 ps |
| T1075 |
/workspace/coverage/default/16.flash_ctrl_sec_info_access.1457126798 |
|
|
Jul 04 05:49:00 PM PDT 24 |
Jul 04 05:50:01 PM PDT 24 |
809984000 ps |
| T1076 |
/workspace/coverage/default/45.flash_ctrl_disable.3157012292 |
|
|
Jul 04 05:51:43 PM PDT 24 |
Jul 04 05:52:06 PM PDT 24 |
13253000 ps |
| T432 |
/workspace/coverage/default/0.flash_ctrl_phy_host_grant_err.1436607641 |
|
|
Jul 04 05:44:29 PM PDT 24 |
Jul 04 05:44:43 PM PDT 24 |
14840900 ps |
| T1077 |
/workspace/coverage/default/2.flash_ctrl_read_word_sweep_serr.626954727 |
|
|
Jul 04 05:45:05 PM PDT 24 |
Jul 04 05:45:28 PM PDT 24 |
26928000 ps |
| T1078 |
/workspace/coverage/default/21.flash_ctrl_disable.2206447850 |
|
|
Jul 04 05:49:49 PM PDT 24 |
Jul 04 05:50:10 PM PDT 24 |
42046900 ps |
| T370 |
/workspace/coverage/default/30.flash_ctrl_sec_info_access.473109909 |
|
|
Jul 04 05:50:40 PM PDT 24 |
Jul 04 05:51:38 PM PDT 24 |
2008229500 ps |
| T420 |
/workspace/coverage/default/24.flash_ctrl_rw_evict.1241673889 |
|
|
Jul 04 05:50:08 PM PDT 24 |
Jul 04 05:50:39 PM PDT 24 |
44737100 ps |
| T1079 |
/workspace/coverage/default/15.flash_ctrl_ro.2354556908 |
|
|
Jul 04 05:48:43 PM PDT 24 |
Jul 04 05:50:39 PM PDT 24 |
828481300 ps |
| T1080 |
/workspace/coverage/default/6.flash_ctrl_fetch_code.3586452389 |
|
|
Jul 04 05:46:29 PM PDT 24 |
Jul 04 05:46:54 PM PDT 24 |
256795000 ps |
| T1081 |
/workspace/coverage/default/15.flash_ctrl_connect.3798219310 |
|
|
Jul 04 05:48:48 PM PDT 24 |
Jul 04 05:49:05 PM PDT 24 |
13576200 ps |
| T1082 |
/workspace/coverage/default/32.flash_ctrl_intr_rd.3881871517 |
|
|
Jul 04 05:50:51 PM PDT 24 |
Jul 04 05:52:49 PM PDT 24 |
966326600 ps |
| T46 |
/workspace/coverage/default/2.flash_ctrl_access_after_disable.4251516184 |
|
|
Jul 04 05:45:21 PM PDT 24 |
Jul 04 05:45:35 PM PDT 24 |
44474700 ps |
| T1083 |
/workspace/coverage/default/10.flash_ctrl_hw_sec_otp.1976954717 |
|
|
Jul 04 05:47:37 PM PDT 24 |
Jul 04 05:48:30 PM PDT 24 |
1803105500 ps |
| T1084 |
/workspace/coverage/default/7.flash_ctrl_intr_wr_slow_flash.1917182830 |
|
|
Jul 04 05:46:56 PM PDT 24 |
Jul 04 05:50:50 PM PDT 24 |
50928004100 ps |
| T1085 |
/workspace/coverage/default/16.flash_ctrl_invalid_op.3966425879 |
|
|
Jul 04 05:48:54 PM PDT 24 |
Jul 04 05:50:08 PM PDT 24 |
1456649800 ps |
| T1086 |
/workspace/coverage/default/4.flash_ctrl_error_mp.2974059666 |
|
|
Jul 04 05:45:50 PM PDT 24 |
Jul 04 06:26:38 PM PDT 24 |
5898738300 ps |
| T1087 |
/workspace/coverage/default/3.flash_ctrl_serr_address.2227757447 |
|
|
Jul 04 05:45:26 PM PDT 24 |
Jul 04 05:46:42 PM PDT 24 |
1765878100 ps |
| T1088 |
/workspace/coverage/default/35.flash_ctrl_rw_evict.3750045206 |
|
|
Jul 04 05:51:02 PM PDT 24 |
Jul 04 05:51:31 PM PDT 24 |
57327500 ps |
| T1089 |
/workspace/coverage/default/13.flash_ctrl_intr_rd.2537641326 |
|
|
Jul 04 05:48:15 PM PDT 24 |
Jul 04 05:50:27 PM PDT 24 |
1951706800 ps |
| T1090 |
/workspace/coverage/default/55.flash_ctrl_connect.1580623139 |
|
|
Jul 04 05:52:06 PM PDT 24 |
Jul 04 05:52:20 PM PDT 24 |
53236600 ps |
| T1091 |
/workspace/coverage/default/15.flash_ctrl_invalid_op.3608724545 |
|
|
Jul 04 05:48:44 PM PDT 24 |
Jul 04 05:49:51 PM PDT 24 |
8373801800 ps |
| T1092 |
/workspace/coverage/default/7.flash_ctrl_sec_info_access.2037429392 |
|
|
Jul 04 05:47:01 PM PDT 24 |
Jul 04 05:47:59 PM PDT 24 |
5674400400 ps |
| T1093 |
/workspace/coverage/default/14.flash_ctrl_ro.1974433971 |
|
|
Jul 04 05:48:28 PM PDT 24 |
Jul 04 05:50:22 PM PDT 24 |
2343529800 ps |
| T1094 |
/workspace/coverage/default/33.flash_ctrl_rw_evict_all_en.3588067210 |
|
|
Jul 04 05:50:57 PM PDT 24 |
Jul 04 05:51:29 PM PDT 24 |
53797300 ps |
| T1095 |
/workspace/coverage/default/0.flash_ctrl_alert_test.733292251 |
|
|
Jul 04 05:44:28 PM PDT 24 |
Jul 04 05:44:42 PM PDT 24 |
58686700 ps |
| T1096 |
/workspace/coverage/default/31.flash_ctrl_intr_rd.1182966858 |
|
|
Jul 04 05:50:40 PM PDT 24 |
Jul 04 05:54:05 PM PDT 24 |
7593141700 ps |
| T1097 |
/workspace/coverage/default/45.flash_ctrl_sec_info_access.3674218248 |
|
|
Jul 04 05:51:43 PM PDT 24 |
Jul 04 05:52:48 PM PDT 24 |
2377093500 ps |
| T1098 |
/workspace/coverage/default/29.flash_ctrl_hw_sec_otp.3220082304 |
|
|
Jul 04 05:50:34 PM PDT 24 |
Jul 04 05:52:37 PM PDT 24 |
1615021100 ps |
| T1099 |
/workspace/coverage/default/8.flash_ctrl_prog_reset.942531541 |
|
|
Jul 04 05:47:11 PM PDT 24 |
Jul 04 05:47:24 PM PDT 24 |
26717200 ps |
| T183 |
/workspace/coverage/default/4.flash_ctrl_hw_rma_reset.2685974376 |
|
|
Jul 04 05:45:42 PM PDT 24 |
Jul 04 06:00:03 PM PDT 24 |
160169694800 ps |
| T336 |
/workspace/coverage/default/35.flash_ctrl_hw_sec_otp.1274103231 |
|
|
Jul 04 05:51:02 PM PDT 24 |
Jul 04 05:52:50 PM PDT 24 |
3962880100 ps |
| T1100 |
/workspace/coverage/default/24.flash_ctrl_alert_test.2275503539 |
|
|
Jul 04 05:50:09 PM PDT 24 |
Jul 04 05:50:23 PM PDT 24 |
84816500 ps |
| T1101 |
/workspace/coverage/default/19.flash_ctrl_lcmgr_intg.79693735 |
|
|
Jul 04 05:49:36 PM PDT 24 |
Jul 04 05:49:50 PM PDT 24 |
15619900 ps |
| T1102 |
/workspace/coverage/default/36.flash_ctrl_rw_evict.2503080721 |
|
|
Jul 04 05:51:04 PM PDT 24 |
Jul 04 05:51:33 PM PDT 24 |
29337700 ps |
| T1103 |
/workspace/coverage/default/0.flash_ctrl_rw_evict.2243378781 |
|
|
Jul 04 05:44:19 PM PDT 24 |
Jul 04 05:44:51 PM PDT 24 |
27610700 ps |
| T1104 |
/workspace/coverage/default/38.flash_ctrl_rw_evict.1817646695 |
|
|
Jul 04 05:51:19 PM PDT 24 |
Jul 04 05:51:51 PM PDT 24 |
44962500 ps |
| T1105 |
/workspace/coverage/default/5.flash_ctrl_rand_ops.2301330539 |
|
|
Jul 04 05:46:10 PM PDT 24 |
Jul 04 05:49:35 PM PDT 24 |
226893200 ps |
| T1106 |
/workspace/coverage/default/18.flash_ctrl_hw_sec_otp.953917120 |
|
|
Jul 04 05:49:14 PM PDT 24 |
Jul 04 05:50:11 PM PDT 24 |
1177716800 ps |
| T1107 |
/workspace/coverage/default/17.flash_ctrl_prog_reset.2820141471 |
|
|
Jul 04 05:49:08 PM PDT 24 |
Jul 04 05:49:22 PM PDT 24 |
57716500 ps |
| T1108 |
/workspace/coverage/default/75.flash_ctrl_otp_reset.1607066311 |
|
|
Jul 04 05:52:20 PM PDT 24 |
Jul 04 05:54:37 PM PDT 24 |
38912300 ps |
| T1109 |
/workspace/coverage/default/54.flash_ctrl_otp_reset.2961416283 |
|
|
Jul 04 05:51:56 PM PDT 24 |
Jul 04 05:54:09 PM PDT 24 |
98240400 ps |
| T256 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.3038861817 |
|
|
Jul 04 05:36:47 PM PDT 24 |
Jul 04 05:37:02 PM PDT 24 |
17980600 ps |
| T1110 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.3803044189 |
|
|
Jul 04 05:36:44 PM PDT 24 |
Jul 04 05:37:01 PM PDT 24 |
27933400 ps |
| T68 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3293041655 |
|
|
Jul 04 05:36:48 PM PDT 24 |
Jul 04 05:37:03 PM PDT 24 |
53039400 ps |
| T95 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1441317029 |
|
|
Jul 04 05:37:05 PM PDT 24 |
Jul 04 05:37:22 PM PDT 24 |
137714600 ps |
| T1111 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1875849758 |
|
|
Jul 04 05:37:03 PM PDT 24 |
Jul 04 05:37:16 PM PDT 24 |
39013800 ps |
| T285 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.1395302433 |
|
|
Jul 04 05:37:21 PM PDT 24 |
Jul 04 05:37:35 PM PDT 24 |
25230100 ps |
| T69 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.636779196 |
|
|
Jul 04 05:37:12 PM PDT 24 |
Jul 04 05:37:28 PM PDT 24 |
130045900 ps |
| T70 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.371411299 |
|
|
Jul 04 05:36:46 PM PDT 24 |
Jul 04 05:37:21 PM PDT 24 |
1512728400 ps |
| T96 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.2454594219 |
|
|
Jul 04 05:36:46 PM PDT 24 |
Jul 04 05:51:45 PM PDT 24 |
1315156600 ps |
| T278 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2998045666 |
|
|
Jul 04 05:36:53 PM PDT 24 |
Jul 04 05:37:34 PM PDT 24 |
338220800 ps |
| T286 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.569861828 |
|
|
Jul 04 05:37:10 PM PDT 24 |
Jul 04 05:37:24 PM PDT 24 |
20957100 ps |
| T276 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.2227154267 |
|
|
Jul 04 05:37:11 PM PDT 24 |
Jul 04 05:37:29 PM PDT 24 |
77958500 ps |
| T277 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3780585027 |
|
|
Jul 04 05:36:50 PM PDT 24 |
Jul 04 05:37:38 PM PDT 24 |
25639900 ps |
| T97 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.2047161435 |
|
|
Jul 04 05:37:10 PM PDT 24 |
Jul 04 05:37:28 PM PDT 24 |
91149100 ps |
| T1112 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.2298170945 |
|
|
Jul 04 05:36:46 PM PDT 24 |
Jul 04 05:37:02 PM PDT 24 |
44510300 ps |
| T339 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.4272008290 |
|
|
Jul 04 05:37:00 PM PDT 24 |
Jul 04 05:37:14 PM PDT 24 |
16477000 ps |
| T243 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.2141090048 |
|
|
Jul 04 05:37:10 PM PDT 24 |
Jul 04 05:37:28 PM PDT 24 |
453856400 ps |
| T244 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2161677665 |
|
|
Jul 04 05:37:02 PM PDT 24 |
Jul 04 05:37:22 PM PDT 24 |
65132100 ps |
| T206 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.116434711 |
|
|
Jul 04 05:36:55 PM PDT 24 |
Jul 04 05:49:42 PM PDT 24 |
4895309000 ps |
| T321 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.3752952226 |
|
|
Jul 04 05:37:18 PM PDT 24 |
Jul 04 05:37:34 PM PDT 24 |
130348800 ps |
| T245 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.2394377562 |
|
|
Jul 04 05:37:09 PM PDT 24 |
Jul 04 05:52:18 PM PDT 24 |
1457200500 ps |
| T322 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1191613375 |
|
|
Jul 04 05:36:47 PM PDT 24 |
Jul 04 05:37:08 PM PDT 24 |
837708300 ps |
| T246 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1404185226 |
|
|
Jul 04 05:37:20 PM PDT 24 |
Jul 04 05:37:38 PM PDT 24 |
94158600 ps |
| T247 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.2228525138 |
|
|
Jul 04 05:37:04 PM PDT 24 |
Jul 04 05:37:20 PM PDT 24 |
70309200 ps |
| T248 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2097545959 |
|
|
Jul 04 05:37:10 PM PDT 24 |
Jul 04 05:37:31 PM PDT 24 |
369855800 ps |
| T340 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.548657195 |
|
|
Jul 04 05:37:20 PM PDT 24 |
Jul 04 05:37:34 PM PDT 24 |
27006000 ps |
| T207 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.3232777463 |
|
|
Jul 04 05:37:09 PM PDT 24 |
Jul 04 05:37:28 PM PDT 24 |
44318000 ps |
| T341 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.2672371172 |
|
|
Jul 04 05:37:26 PM PDT 24 |
Jul 04 05:37:40 PM PDT 24 |
15446400 ps |
| T1113 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.4152080017 |
|
|
Jul 04 05:37:16 PM PDT 24 |
Jul 04 05:37:47 PM PDT 24 |
806182200 ps |
| T1114 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.4132928199 |
|
|
Jul 04 05:36:51 PM PDT 24 |
Jul 04 05:37:05 PM PDT 24 |
11447300 ps |
| T249 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.2295432923 |
|
|
Jul 04 05:36:45 PM PDT 24 |
Jul 04 05:52:11 PM PDT 24 |
670396300 ps |
| T1115 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2884686516 |
|
|
Jul 04 05:36:47 PM PDT 24 |
Jul 04 05:37:34 PM PDT 24 |
273203300 ps |
| T291 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.2690625990 |
|
|
Jul 04 05:37:06 PM PDT 24 |
Jul 04 05:49:46 PM PDT 24 |
1270687300 ps |
| T1116 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1446971665 |
|
|
Jul 04 05:37:09 PM PDT 24 |
Jul 04 05:37:25 PM PDT 24 |
143018400 ps |
| T342 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.1205343592 |
|
|
Jul 04 05:37:19 PM PDT 24 |
Jul 04 05:37:33 PM PDT 24 |
166535900 ps |
| T1117 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1906461802 |
|
|
Jul 04 05:36:47 PM PDT 24 |
Jul 04 05:37:46 PM PDT 24 |
1089905300 ps |
| T343 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.3779068978 |
|
|
Jul 04 05:36:56 PM PDT 24 |
Jul 04 05:37:10 PM PDT 24 |
27245500 ps |
| T288 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.2871379812 |
|
|
Jul 04 05:36:46 PM PDT 24 |
Jul 04 05:37:05 PM PDT 24 |
194658200 ps |
| T1118 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2899828225 |
|
|
Jul 04 05:37:10 PM PDT 24 |
Jul 04 05:37:27 PM PDT 24 |
94982700 ps |
| T1119 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.3463727900 |
|
|
Jul 04 05:36:46 PM PDT 24 |
Jul 04 05:37:00 PM PDT 24 |
14028700 ps |
| T344 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3797527087 |
|
|
Jul 04 05:37:22 PM PDT 24 |
Jul 04 05:37:36 PM PDT 24 |
15655100 ps |
| T1120 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.2831421842 |
|
|
Jul 04 05:37:19 PM PDT 24 |
Jul 04 05:37:33 PM PDT 24 |
17978800 ps |
| T1121 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.814050326 |
|
|
Jul 04 05:37:01 PM PDT 24 |
Jul 04 05:37:17 PM PDT 24 |
40504200 ps |
| T1122 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.822353943 |
|
|
Jul 04 05:37:23 PM PDT 24 |
Jul 04 05:37:37 PM PDT 24 |
14870000 ps |
| T1123 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.724748008 |
|
|
Jul 04 05:36:44 PM PDT 24 |
Jul 04 05:37:23 PM PDT 24 |
1288398200 ps |
| T1124 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.1655074189 |
|
|
Jul 04 05:36:44 PM PDT 24 |
Jul 04 05:36:58 PM PDT 24 |
17696000 ps |
| T290 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.813800105 |
|
|
Jul 04 05:37:16 PM PDT 24 |
Jul 04 05:52:42 PM PDT 24 |
1009644000 ps |
| T1125 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3194531527 |
|
|
Jul 04 05:36:52 PM PDT 24 |
Jul 04 05:37:12 PM PDT 24 |
112996000 ps |
| T1126 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.3322739079 |
|
|
Jul 04 05:36:58 PM PDT 24 |
Jul 04 05:37:14 PM PDT 24 |
19032500 ps |
| T1127 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.3617625866 |
|
|
Jul 04 05:37:16 PM PDT 24 |
Jul 04 05:37:30 PM PDT 24 |
17134500 ps |
| T323 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.805499283 |
|
|
Jul 04 05:36:59 PM PDT 24 |
Jul 04 05:37:16 PM PDT 24 |
1593003400 ps |
| T1128 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.95515541 |
|
|
Jul 04 05:36:49 PM PDT 24 |
Jul 04 05:37:03 PM PDT 24 |
32395900 ps |
| T1129 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.655015760 |
|
|
Jul 04 05:36:59 PM PDT 24 |
Jul 04 05:37:17 PM PDT 24 |
25610600 ps |
| T1130 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.1176324110 |
|
|
Jul 04 05:37:24 PM PDT 24 |
Jul 04 05:37:38 PM PDT 24 |
49624900 ps |
| T1131 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.739947342 |
|
|
Jul 04 05:37:10 PM PDT 24 |
Jul 04 05:37:27 PM PDT 24 |
123495600 ps |
| T297 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1701643161 |
|
|
Jul 04 05:36:57 PM PDT 24 |
Jul 04 05:37:16 PM PDT 24 |
48467400 ps |
| T1132 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.2823420591 |
|
|
Jul 04 05:37:11 PM PDT 24 |
Jul 04 05:37:27 PM PDT 24 |
37194200 ps |
| T1133 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.3120039249 |
|
|
Jul 04 05:37:17 PM PDT 24 |
Jul 04 05:37:31 PM PDT 24 |
65164900 ps |
| T354 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.328454978 |
|
|
Jul 04 05:36:45 PM PDT 24 |
Jul 04 05:37:03 PM PDT 24 |
27949200 ps |
| T1134 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.418780842 |
|
|
Jul 04 05:37:00 PM PDT 24 |
Jul 04 05:37:34 PM PDT 24 |
223082900 ps |
| T1135 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.2170124533 |
|
|
Jul 04 05:36:44 PM PDT 24 |
Jul 04 05:37:01 PM PDT 24 |
14744000 ps |
| T1136 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.3826119495 |
|
|
Jul 04 05:36:47 PM PDT 24 |
Jul 04 05:37:53 PM PDT 24 |
801895800 ps |
| T1137 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1903322562 |
|
|
Jul 04 05:37:05 PM PDT 24 |
Jul 04 05:37:22 PM PDT 24 |
13460500 ps |
| T1138 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2192139857 |
|
|
Jul 04 05:36:49 PM PDT 24 |
Jul 04 05:37:02 PM PDT 24 |
28815500 ps |
| T1139 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.3362898820 |
|
|
Jul 04 05:36:52 PM PDT 24 |
Jul 04 05:37:12 PM PDT 24 |
236456000 ps |
| T324 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.587090061 |
|
|
Jul 04 05:36:45 PM PDT 24 |
Jul 04 05:37:58 PM PDT 24 |
3380564300 ps |
| T1140 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.1084305271 |
|
|
Jul 04 05:36:49 PM PDT 24 |
Jul 04 05:37:43 PM PDT 24 |
5976887000 ps |
| T257 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2848088352 |
|
|
Jul 04 05:36:47 PM PDT 24 |
Jul 04 05:37:01 PM PDT 24 |
45015100 ps |
| T1141 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.3762809406 |
|
|
Jul 04 05:36:52 PM PDT 24 |
Jul 04 05:37:08 PM PDT 24 |
47860700 ps |
| T1142 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3384204024 |
|
|
Jul 04 05:37:21 PM PDT 24 |
Jul 04 05:37:34 PM PDT 24 |
44723700 ps |
| T1143 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.2900557968 |
|
|
Jul 04 05:36:56 PM PDT 24 |
Jul 04 05:37:12 PM PDT 24 |
92412400 ps |
| T1144 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3836865442 |
|
|
Jul 04 05:37:09 PM PDT 24 |
Jul 04 05:37:26 PM PDT 24 |
23714300 ps |
| T353 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.61498192 |
|
|
Jul 04 05:36:46 PM PDT 24 |
Jul 04 05:37:03 PM PDT 24 |
131225700 ps |
| T1145 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.1364913501 |
|
|
Jul 04 05:37:00 PM PDT 24 |
Jul 04 05:37:13 PM PDT 24 |
45499200 ps |
| T1146 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1347004526 |
|
|
Jul 04 05:36:51 PM PDT 24 |
Jul 04 05:37:08 PM PDT 24 |
78026000 ps |
| T1147 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.3194985464 |
|
|
Jul 04 05:36:47 PM PDT 24 |
Jul 04 05:37:43 PM PDT 24 |
8196737800 ps |
| T356 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3303076048 |
|
|
Jul 04 05:37:17 PM PDT 24 |
Jul 04 05:43:46 PM PDT 24 |
1734827800 ps |
| T1148 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.3476187572 |
|
|
Jul 04 05:37:21 PM PDT 24 |
Jul 04 05:37:34 PM PDT 24 |
17879100 ps |
| T283 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.3716907648 |
|
|
Jul 04 05:36:52 PM PDT 24 |
Jul 04 05:37:09 PM PDT 24 |
76812300 ps |
| T1149 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.1236803978 |
|
|
Jul 04 05:36:46 PM PDT 24 |
Jul 04 05:37:02 PM PDT 24 |
17835900 ps |
| T325 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1220148012 |
|
|
Jul 04 05:36:59 PM PDT 24 |
Jul 04 05:38:03 PM PDT 24 |
6182891100 ps |
| T287 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.1631361298 |
|
|
Jul 04 05:36:49 PM PDT 24 |
Jul 04 05:49:22 PM PDT 24 |
1693990200 ps |
| T1150 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.887744879 |
|
|
Jul 04 05:37:00 PM PDT 24 |
Jul 04 05:37:16 PM PDT 24 |
11368900 ps |
| T1151 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1634931761 |
|
|
Jul 04 05:36:52 PM PDT 24 |
Jul 04 05:37:08 PM PDT 24 |
124843300 ps |
| T281 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.3697634028 |
|
|
Jul 04 05:36:56 PM PDT 24 |
Jul 04 05:37:14 PM PDT 24 |
69443600 ps |
| T1152 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.1697615824 |
|
|
Jul 04 05:37:18 PM PDT 24 |
Jul 04 05:37:32 PM PDT 24 |
47459600 ps |
| T1153 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.99714762 |
|
|
Jul 04 05:36:48 PM PDT 24 |
Jul 04 05:37:02 PM PDT 24 |
16046000 ps |
| T326 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2640828328 |
|
|
Jul 04 05:36:49 PM PDT 24 |
Jul 04 05:37:09 PM PDT 24 |
358355300 ps |
| T279 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3730727801 |
|
|
Jul 04 05:36:49 PM PDT 24 |
Jul 04 05:37:08 PM PDT 24 |
81894900 ps |
| T1154 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.2846542040 |
|
|
Jul 04 05:37:01 PM PDT 24 |
Jul 04 05:37:15 PM PDT 24 |
14306000 ps |
| T360 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.696021570 |
|
|
Jul 04 05:37:17 PM PDT 24 |
Jul 04 05:43:45 PM PDT 24 |
360831000 ps |
| T1155 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.2161744808 |
|
|
Jul 04 05:36:47 PM PDT 24 |
Jul 04 05:37:01 PM PDT 24 |
14657400 ps |
| T299 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.813361605 |
|
|
Jul 04 05:37:06 PM PDT 24 |
Jul 04 05:52:15 PM PDT 24 |
346237100 ps |
| T284 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.2637523558 |
|
|
Jul 04 05:37:09 PM PDT 24 |
Jul 04 05:37:28 PM PDT 24 |
110632500 ps |
| T1156 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.3005262572 |
|
|
Jul 04 05:36:45 PM PDT 24 |
Jul 04 05:37:12 PM PDT 24 |
34483400 ps |
| T1157 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1609266449 |
|
|
Jul 04 05:37:18 PM PDT 24 |
Jul 04 05:37:35 PM PDT 24 |
188224900 ps |
| T1158 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.2684761535 |
|
|
Jul 04 05:37:01 PM PDT 24 |
Jul 04 05:37:20 PM PDT 24 |
39157800 ps |
| T280 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.1309369491 |
|
|
Jul 04 05:36:39 PM PDT 24 |
Jul 04 05:36:59 PM PDT 24 |
81023900 ps |
| T1159 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.749063082 |
|
|
Jul 04 05:37:19 PM PDT 24 |
Jul 04 05:37:33 PM PDT 24 |
17123000 ps |
| T282 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.871732182 |
|
|
Jul 04 05:37:11 PM PDT 24 |
Jul 04 05:37:30 PM PDT 24 |
92410300 ps |
| T1160 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.3443889552 |
|
|
Jul 04 05:36:45 PM PDT 24 |
Jul 04 05:37:01 PM PDT 24 |
98469400 ps |
| T1161 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1686661335 |
|
|
Jul 04 05:36:48 PM PDT 24 |
Jul 04 05:37:05 PM PDT 24 |
171480700 ps |
| T258 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3127568053 |
|
|
Jul 04 05:36:46 PM PDT 24 |
Jul 04 05:37:00 PM PDT 24 |
282885800 ps |
| T1162 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.4137426240 |
|
|
Jul 04 05:37:19 PM PDT 24 |
Jul 04 05:37:34 PM PDT 24 |
27141400 ps |
| T1163 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3184455885 |
|
|
Jul 04 05:37:11 PM PDT 24 |
Jul 04 05:37:27 PM PDT 24 |
17418000 ps |
| T1164 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.1768873731 |
|
|
Jul 04 05:37:10 PM PDT 24 |
Jul 04 05:37:25 PM PDT 24 |
45644000 ps |
| T357 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.3870984214 |
|
|
Jul 04 05:37:02 PM PDT 24 |
Jul 04 05:44:49 PM PDT 24 |
1667749800 ps |
| T1165 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.3519111354 |
|
|
Jul 04 05:36:45 PM PDT 24 |
Jul 04 05:36:58 PM PDT 24 |
28502800 ps |
| T1166 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.2134934329 |
|
|
Jul 04 05:37:01 PM PDT 24 |
Jul 04 05:37:16 PM PDT 24 |
291215300 ps |
| T1167 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.2037249087 |
|
|
Jul 04 05:36:47 PM PDT 24 |
Jul 04 05:37:07 PM PDT 24 |
196071000 ps |
| T1168 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2501531514 |
|
|
Jul 04 05:37:08 PM PDT 24 |
Jul 04 05:37:25 PM PDT 24 |
14154400 ps |
| T1169 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3858513270 |
|
|
Jul 04 05:37:09 PM PDT 24 |
Jul 04 05:37:24 PM PDT 24 |
14664000 ps |
| T292 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.3673412943 |
|
|
Jul 04 05:36:51 PM PDT 24 |
Jul 04 05:37:07 PM PDT 24 |
109731400 ps |
| T358 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.1388361954 |
|
|
Jul 04 05:36:59 PM PDT 24 |
Jul 04 05:44:36 PM PDT 24 |
1378699200 ps |
| T1170 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.1929104995 |
|
|
Jul 04 05:37:18 PM PDT 24 |
Jul 04 05:37:32 PM PDT 24 |
17256400 ps |
| T298 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2849801339 |
|
|
Jul 04 05:36:45 PM PDT 24 |
Jul 04 05:51:44 PM PDT 24 |
1624062800 ps |
| T1171 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.1645386539 |
|
|
Jul 04 05:37:10 PM PDT 24 |
Jul 04 05:37:24 PM PDT 24 |
42374200 ps |
| T295 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.16251988 |
|
|
Jul 04 05:36:49 PM PDT 24 |
Jul 04 05:37:09 PM PDT 24 |
154750900 ps |
| T1172 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1213082579 |
|
|
Jul 04 05:37:17 PM PDT 24 |
Jul 04 05:37:33 PM PDT 24 |
37720600 ps |
| T1173 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.2922088130 |
|
|
Jul 04 05:37:16 PM PDT 24 |
Jul 04 05:37:32 PM PDT 24 |
26275600 ps |
| T359 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.3925298401 |
|
|
Jul 04 05:36:52 PM PDT 24 |
Jul 04 05:51:51 PM PDT 24 |
733853800 ps |
| T1174 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.542368787 |
|
|
Jul 04 05:36:53 PM PDT 24 |
Jul 04 05:37:09 PM PDT 24 |
13187100 ps |
| T1175 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1997932714 |
|
|
Jul 04 05:36:43 PM PDT 24 |
Jul 04 05:37:01 PM PDT 24 |
247711800 ps |
| T1176 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.407034100 |
|
|
Jul 04 05:37:10 PM PDT 24 |
Jul 04 05:37:28 PM PDT 24 |
37528800 ps |
| T1177 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.896033940 |
|
|
Jul 04 05:36:44 PM PDT 24 |
Jul 04 05:37:01 PM PDT 24 |
46457300 ps |
| T1178 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.148376457 |
|
|
Jul 04 05:37:04 PM PDT 24 |
Jul 04 05:37:20 PM PDT 24 |
30395600 ps |
| T1179 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1090342512 |
|
|
Jul 04 05:37:19 PM PDT 24 |
Jul 04 05:37:36 PM PDT 24 |
18133800 ps |
| T1180 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.1121501654 |
|
|
Jul 04 05:37:17 PM PDT 24 |
Jul 04 05:37:30 PM PDT 24 |
44869900 ps |
| T1181 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1874240726 |
|
|
Jul 04 05:37:08 PM PDT 24 |
Jul 04 05:37:24 PM PDT 24 |
372445700 ps |
| T1182 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3911716521 |
|
|
Jul 04 05:37:17 PM PDT 24 |
Jul 04 05:37:31 PM PDT 24 |
136322100 ps |
| T296 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.3037972368 |
|
|
Jul 04 05:37:17 PM PDT 24 |
Jul 04 05:37:36 PM PDT 24 |
97498200 ps |
| T1183 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.1281017579 |
|
|
Jul 04 05:37:01 PM PDT 24 |
Jul 04 05:37:15 PM PDT 24 |
51754800 ps |
| T327 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2892600022 |
|
|
Jul 04 05:37:11 PM PDT 24 |
Jul 04 05:37:30 PM PDT 24 |
418216700 ps |
| T259 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.3611727820 |
|
|
Jul 04 05:36:47 PM PDT 24 |
Jul 04 05:37:01 PM PDT 24 |
15573800 ps |
| T1184 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.827913895 |
|
|
Jul 04 05:37:13 PM PDT 24 |
Jul 04 05:37:29 PM PDT 24 |
76962900 ps |
| T293 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.897231189 |
|
|
Jul 04 05:37:13 PM PDT 24 |
Jul 04 05:37:32 PM PDT 24 |
316876800 ps |
| T1185 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.4063984951 |
|
|
Jul 04 05:37:10 PM PDT 24 |
Jul 04 05:37:26 PM PDT 24 |
308086300 ps |
| T1186 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.2660085622 |
|
|
Jul 04 05:37:24 PM PDT 24 |
Jul 04 05:37:38 PM PDT 24 |
16668300 ps |
| T1187 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.1150995034 |
|
|
Jul 04 05:36:45 PM PDT 24 |
Jul 04 05:37:01 PM PDT 24 |
18221300 ps |
| T1188 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2640286405 |
|
|
Jul 04 05:37:23 PM PDT 24 |
Jul 04 05:37:37 PM PDT 24 |
30917400 ps |
| T1189 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.1511922916 |
|
|
Jul 04 05:36:54 PM PDT 24 |
Jul 04 05:37:08 PM PDT 24 |
40717500 ps |
| T1190 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.1669557986 |
|
|
Jul 04 05:37:18 PM PDT 24 |
Jul 04 05:37:31 PM PDT 24 |
50551000 ps |
| T1191 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2336323651 |
|
|
Jul 04 05:37:17 PM PDT 24 |
Jul 04 05:37:33 PM PDT 24 |
147494500 ps |
| T1192 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2444605109 |
|
|
Jul 04 05:37:10 PM PDT 24 |
Jul 04 05:37:26 PM PDT 24 |
37909300 ps |
| T1193 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.3124318956 |
|
|
Jul 04 05:37:23 PM PDT 24 |
Jul 04 05:37:40 PM PDT 24 |
13813400 ps |
| T1194 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1502416054 |
|
|
Jul 04 05:36:46 PM PDT 24 |
Jul 04 05:37:00 PM PDT 24 |
37793500 ps |
| T1195 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.1887390562 |
|
|
Jul 04 05:37:23 PM PDT 24 |
Jul 04 05:37:38 PM PDT 24 |
17860900 ps |
| T1196 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.3444295558 |
|
|
Jul 04 05:36:56 PM PDT 24 |
Jul 04 05:37:09 PM PDT 24 |
94598100 ps |
| T1197 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.2151882613 |
|
|
Jul 04 05:37:01 PM PDT 24 |
Jul 04 05:37:19 PM PDT 24 |
177898400 ps |
| T1198 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1715600919 |
|
|
Jul 04 05:37:10 PM PDT 24 |
Jul 04 05:37:41 PM PDT 24 |
123351700 ps |
| T1199 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3033653748 |
|
|
Jul 04 05:37:09 PM PDT 24 |
Jul 04 05:37:24 PM PDT 24 |
33740000 ps |
| T1200 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2396458970 |
|
|
Jul 04 05:37:10 PM PDT 24 |
Jul 04 05:37:27 PM PDT 24 |
21352200 ps |
| T1201 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.3682799379 |
|
|
Jul 04 05:36:48 PM PDT 24 |
Jul 04 05:38:01 PM PDT 24 |
2430164000 ps |
| T1202 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1433542302 |
|
|
Jul 04 05:37:17 PM PDT 24 |
Jul 04 05:37:35 PM PDT 24 |
92238000 ps |
| T1203 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3356719565 |
|
|
Jul 04 05:37:10 PM PDT 24 |
Jul 04 05:37:27 PM PDT 24 |
195686000 ps |
| T1204 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.3062295964 |
|
|
Jul 04 05:37:19 PM PDT 24 |
Jul 04 05:37:33 PM PDT 24 |
14209800 ps |
| T1205 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.2718792288 |
|
|
Jul 04 05:37:19 PM PDT 24 |
Jul 04 05:37:33 PM PDT 24 |
61629100 ps |
| T1206 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.3852312597 |
|
|
Jul 04 05:36:48 PM PDT 24 |
Jul 04 05:44:30 PM PDT 24 |
2008079400 ps |
| T1207 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.4054831111 |
|
|
Jul 04 05:36:53 PM PDT 24 |
Jul 04 05:37:07 PM PDT 24 |
27480400 ps |
| T260 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.4127950775 |
|
|
Jul 04 05:36:53 PM PDT 24 |
Jul 04 05:37:08 PM PDT 24 |
22053000 ps |
| T1208 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.434290818 |
|
|
Jul 04 05:37:18 PM PDT 24 |
Jul 04 05:37:36 PM PDT 24 |
150624900 ps |
| T1209 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3097876688 |
|
|
Jul 04 05:37:21 PM PDT 24 |
Jul 04 05:37:41 PM PDT 24 |
317138200 ps |
| T1210 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.860177903 |
|
|
Jul 04 05:37:26 PM PDT 24 |
Jul 04 05:37:39 PM PDT 24 |
49934800 ps |
| T1211 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.263884420 |
|
|
Jul 04 05:36:47 PM PDT 24 |
Jul 04 05:37:01 PM PDT 24 |
28251500 ps |
| T1212 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.4133915457 |
|
|
Jul 04 05:37:10 PM PDT 24 |
Jul 04 05:44:53 PM PDT 24 |
708738500 ps |
| T294 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.562965472 |
|
|
Jul 04 05:37:19 PM PDT 24 |
Jul 04 05:37:39 PM PDT 24 |
512411700 ps |
| T1213 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.1797448232 |
|
|
Jul 04 05:36:45 PM PDT 24 |
Jul 04 05:37:17 PM PDT 24 |
28195600 ps |
| T1214 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.1113552944 |
|
|
Jul 04 05:37:21 PM PDT 24 |
Jul 04 05:37:35 PM PDT 24 |
42643900 ps |
| T1215 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3639495445 |
|
|
Jul 04 05:37:22 PM PDT 24 |
Jul 04 05:37:38 PM PDT 24 |
24313400 ps |
| T1216 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.1456158104 |
|
|
Jul 04 05:36:54 PM PDT 24 |
Jul 04 05:37:11 PM PDT 24 |
193108100 ps |
| T1217 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3788609897 |
|
|
Jul 04 05:36:46 PM PDT 24 |
Jul 04 05:37:07 PM PDT 24 |
212211600 ps |
| T1218 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.1136933986 |
|
|
Jul 04 05:37:10 PM PDT 24 |
Jul 04 05:37:24 PM PDT 24 |
27174200 ps |
| T1219 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.951392799 |
|
|
Jul 04 05:36:45 PM PDT 24 |
Jul 04 05:37:02 PM PDT 24 |
41247000 ps |
| T1220 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.900659279 |
|
|
Jul 04 05:36:51 PM PDT 24 |
Jul 04 05:37:06 PM PDT 24 |
225719200 ps |
| T1221 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.866519020 |
|
|
Jul 04 05:37:10 PM PDT 24 |
Jul 04 05:37:27 PM PDT 24 |
82895400 ps |
| T1222 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.3522733588 |
|
|
Jul 04 05:37:20 PM PDT 24 |
Jul 04 05:37:33 PM PDT 24 |
24583000 ps |
| T1223 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2947094366 |
|
|
Jul 04 05:37:09 PM PDT 24 |
Jul 04 05:37:23 PM PDT 24 |
58673700 ps |
| T328 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3701780904 |
|
|
Jul 04 05:36:54 PM PDT 24 |
Jul 04 05:37:34 PM PDT 24 |
94633400 ps |
| T355 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.364647515 |
|
|
Jul 04 05:37:09 PM PDT 24 |
Jul 04 05:44:59 PM PDT 24 |
5496849200 ps |
| T1224 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1499748181 |
|
|
Jul 04 05:37:18 PM PDT 24 |
Jul 04 05:37:32 PM PDT 24 |
16879900 ps |
| T1225 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.2283216381 |
|
|
Jul 04 05:37:01 PM PDT 24 |
Jul 04 05:37:20 PM PDT 24 |
58437400 ps |
| T1226 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.3014554458 |
|
|
Jul 04 05:37:00 PM PDT 24 |
Jul 04 05:37:18 PM PDT 24 |
229842000 ps |
| T1227 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.667361442 |
|
|
Jul 04 05:36:52 PM PDT 24 |
Jul 04 05:37:05 PM PDT 24 |
37529900 ps |
| T1228 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.3134864485 |
|
|
Jul 04 05:37:17 PM PDT 24 |
Jul 04 05:37:31 PM PDT 24 |
15023300 ps |
| T1229 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.279894227 |
|
|
Jul 04 05:37:10 PM PDT 24 |
Jul 04 05:37:31 PM PDT 24 |
268189100 ps |
| T1230 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.3065231838 |
|
|
Jul 04 05:37:19 PM PDT 24 |
Jul 04 05:37:34 PM PDT 24 |
30184600 ps |
| T1231 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.1408575142 |
|
|
Jul 04 05:37:05 PM PDT 24 |
Jul 04 05:37:22 PM PDT 24 |
72372800 ps |
| T1232 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2328754271 |
|
|
Jul 04 05:37:26 PM PDT 24 |
Jul 04 05:37:39 PM PDT 24 |
59246400 ps |
| T1233 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.515652524 |
|
|
Jul 04 05:37:23 PM PDT 24 |
Jul 04 05:37:37 PM PDT 24 |
22741900 ps |
| T1234 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.781681228 |
|
|
Jul 04 05:36:51 PM PDT 24 |
Jul 04 05:44:31 PM PDT 24 |
807291300 ps |
| T1235 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.3025283921 |
|
|
Jul 04 05:37:19 PM PDT 24 |
Jul 04 05:37:39 PM PDT 24 |
1056941800 ps |
| T1236 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3972179616 |
|
|
Jul 04 05:36:45 PM PDT 24 |
Jul 04 05:37:03 PM PDT 24 |
67869100 ps |
| T1237 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2793741920 |
|
|
Jul 04 05:36:50 PM PDT 24 |
Jul 04 05:37:04 PM PDT 24 |
50993800 ps |
| T1238 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.58688342 |
|
|
Jul 04 05:37:09 PM PDT 24 |
Jul 04 05:49:58 PM PDT 24 |
901386700 ps |
| T1239 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3396111538 |
|
|
Jul 04 05:37:01 PM PDT 24 |
Jul 04 05:37:17 PM PDT 24 |
13788300 ps |
| T1240 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.3469805575 |
|
|
Jul 04 05:37:11 PM PDT 24 |
Jul 04 05:37:29 PM PDT 24 |
91371000 ps |
| T1241 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1541883324 |
|
|
Jul 04 05:36:57 PM PDT 24 |
Jul 04 05:37:34 PM PDT 24 |
222705300 ps |
| T1242 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.977166236 |
|
|
Jul 04 05:36:49 PM PDT 24 |
Jul 04 05:37:09 PM PDT 24 |
80632100 ps |
| T1243 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.467972383 |
|
|
Jul 04 05:37:10 PM PDT 24 |
Jul 04 05:37:25 PM PDT 24 |
24188800 ps |
| T1244 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.3603625716 |
|
|
Jul 04 05:37:04 PM PDT 24 |
Jul 04 05:37:20 PM PDT 24 |
52678400 ps |
| T1245 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1643359881 |
|
|
Jul 04 05:36:48 PM PDT 24 |
Jul 04 05:37:06 PM PDT 24 |
92448100 ps |
| T1246 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3174691490 |
|
|
Jul 04 05:37:10 PM PDT 24 |
Jul 04 05:37:28 PM PDT 24 |
108752800 ps |
| T1247 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1606945876 |
|
|
Jul 04 05:36:49 PM PDT 24 |
Jul 04 05:37:06 PM PDT 24 |
188219500 ps |
| T1248 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.2996943816 |
|
|
Jul 04 05:37:01 PM PDT 24 |
Jul 04 05:37:19 PM PDT 24 |
178497400 ps |
| T1249 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.1622604013 |
|
|
Jul 04 05:37:06 PM PDT 24 |
Jul 04 05:37:23 PM PDT 24 |
21247700 ps |
| T1250 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.704060960 |
|
|
Jul 04 05:37:10 PM PDT 24 |
Jul 04 05:37:29 PM PDT 24 |
520687700 ps |
| T1251 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2493014759 |
|
|
Jul 04 05:37:26 PM PDT 24 |
Jul 04 05:37:39 PM PDT 24 |
118907300 ps |