Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	372045	1		T1	1		T2	272		T3	1
all_values[1]	372045	1		T1	1		T2	272		T3	1
all_values[2]	372045	1		T1	1		T2	272		T3	1
all_values[3]	372045	1		T1	1		T2	272		T3	1
all_values[4]	372045	1		T1	1		T2	272		T3	1
all_values[5]	372045	1		T1	1		T2	272		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	750318	1		T1	6		T2	548		T3	6
auto[1]	1481952	1		T2	1084		T29	6236		T31	6372

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1095807	1		T1	4		T2	815		T3	4
auto[1]	1136463	1		T1	2		T2	817		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	371894	1		T1	1		T2	272		T3	1
all_values[0]	auto[1]	auto[1]	151	1		T251	4		T252	3		T318	1
all_values[1]	auto[0]	auto[1]	371883	1		T1	1		T2	272		T3	1
all_values[1]	auto[1]	auto[1]	162	1		T251	2		T252	6		T318	1
all_values[2]	auto[0]	auto[0]	1576	1		T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	52	1		T252	1		T318	4		T320	1
all_values[2]	auto[1]	auto[0]	370359	1		T2	271		T29	1559		T31	1593
all_values[2]	auto[1]	auto[1]	58	1		T252	3		T319	1		T322	1
all_values[3]	auto[0]	auto[0]	1578	1		T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	56	1		T251	2		T252	3		T318	4
all_values[3]	auto[1]	auto[0]	87329	1		T2	89		T29	1559		T31	1593
all_values[3]	auto[1]	auto[1]	283082	1		T2	182		T37	6168		T26	1639
all_values[4]	auto[0]	auto[0]	1112	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	515	1		T5	1		T22	1		T23	1
all_values[4]	auto[1]	auto[0]	261994	1		T2	180		T29	1		T31	1
all_values[4]	auto[1]	auto[1]	108424	1		T2	91		T29	1558		T31	1592
all_values[5]	auto[0]	auto[0]	1530	1		T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	122	1		T38	1		T39	1		T40	1
all_values[5]	auto[1]	auto[0]	370329	1		T2	271		T29	1559		T31	1593
all_values[5]	auto[1]	auto[1]	64	1		T251	2		T252	1		T319	3