Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	239215	1		T1	4		T2	53		T4	1187
auto[FlashEraseBank]	262517	1		T1	5		T2	38		T5	1135

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	254408	1		T1	8		T2	91		T4	601
auto[FlashOpProgram]	227298	1		T1	1		T4	293		T5	420
auto[FlashOpErase]	16026	1		T4	293		T5	46		T22	2
auto[FlashOpInvalid]	4000	1		T141	200		T279	200		T219	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	254408	1		T1	8		T2	91		T4	601
op[FlashOpProgram]	227298	1		T1	1		T4	293		T5	420
op[FlashOpErase]	16026	1		T4	293		T5	46		T22	2
read_erase_read	568	1		T5	6		T23	4		T33	2
read_prog_read	779	1		T1	1		T5	6		T23	3

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	361096	1		T1	5		T5	100		T22	1
auto[FlashPartInfo]	137299	1		T1	3		T4	1187		T5	1135
auto[FlashPartInfo1]	866	1		T2	40		T83	13		T62	1
auto[FlashPartInfo2]	2471	1		T1	1		T2	51		T64	1

---

Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	182865	1		T1	4		T5	33		T23	27
auto[FlashPartData]	auto[FlashOpProgram]	170706	1		T1	1		T5	36		T23	36
auto[FlashPartData]	auto[FlashOpErase]	3595	1		T5	31		T22	1		T23	34
auto[FlashPartData]	auto[FlashOpInvalid]	3930	1		T141	196		T279	196		T219	198
auto[FlashPartInfo]	auto[FlashOpRead]	69304	1		T1	3		T4	601		T5	736
auto[FlashPartInfo]	auto[FlashOpProgram]	55543	1		T4	293		T5	384		T23	448
auto[FlashPartInfo]	auto[FlashOpErase]	12400	1		T4	293		T5	15		T22	1
auto[FlashPartInfo]	auto[FlashOpInvalid]	52	1		T141	4		T279	4		T219	2
auto[FlashPartInfo1]	auto[FlashOpRead]	696	1		T2	40		T83	13		T62	1
auto[FlashPartInfo1]	auto[FlashOpProgram]	163	1		T133	32		T134	32		T136	1
auto[FlashPartInfo1]	auto[FlashOpErase]	5	1		T136	1		T137	1		T385	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	2	1		T136	2		-	-		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1543	1		T1	1		T2	51		T12	1
auto[FlashPartInfo2]	auto[FlashOpProgram]	886	1		T64	1		T8	5		T83	3
auto[FlashPartInfo2]	auto[FlashOpErase]	26	1		T83	1		T139	1		T216	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	16	1		T404	2		T405	2		T406	4