Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.62	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	1	31	96.88

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	1	31	96.88	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31596	1		T4	624		T5	32		T23	12
auto[1]	65	1		T216	6		T203	7		T84	6
auto[2]	68	1		T179	8		T207	2		T343	1
auto[3]	252	1		T62	5		T30	1		T199	1

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	8004	1		T4	156		T5	8		T23	3
evic_idx[1]	7991	1		T4	156		T5	8		T23	3
evic_idx[2]	7995	1		T4	156		T5	8		T23	3
evic_idx[3]	7991	1		T4	156		T5	8		T23	3

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	31025	1		T4	624		T6	264		T61	492
evic_op[2]	347	1		T23	4		T62	5		T63	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	1	31	96.88	1

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[2]]	[evic_op[2]]	[auto[2]]	0	1	1

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7686	1		T4	156		T6	66		T61	123
evic_idx[0]	evic_op[1]	auto[1]	11	1		T216	2		T203	2		T344	1
evic_idx[0]	evic_op[1]	auto[2]	10	1		T207	1		T345	2		T344	6
evic_idx[0]	evic_op[1]	auto[3]	56	1		T216	5		T213	4		T207	5
evic_idx[0]	evic_op[2]	auto[0]	64	1		T23	1		T224	1		T214	9
evic_idx[0]	evic_op[2]	auto[1]	3	1		T84	1		T346	1		T347	1
evic_idx[0]	evic_op[2]	auto[2]	2	1		T217	2		-	-		-	-
evic_idx[0]	evic_op[2]	auto[3]	19	1		T62	2		T195	1		T343	1
evic_idx[1]	evic_op[1]	auto[0]	7688	1		T4	156		T6	66		T61	123
evic_idx[1]	evic_op[1]	auto[1]	9	1		T216	1		T203	2		T348	2
evic_idx[1]	evic_op[1]	auto[2]	8	1		T207	1		T345	2		T344	4
evic_idx[1]	evic_op[1]	auto[3]	46	1		T216	2		T213	4		T203	2
evic_idx[1]	evic_op[2]	auto[0]	66	1		T23	1		T63	1		T224	1
evic_idx[1]	evic_op[2]	auto[1]	7	1		T84	2		T266	1		T346	3
evic_idx[1]	evic_op[2]	auto[2]	3	1		T349	2		T350	1		-	-
evic_idx[1]	evic_op[2]	auto[3]	12	1		T62	1		T30	1		T210	1
evic_idx[2]	evic_op[1]	auto[0]	7695	1		T4	156		T6	66		T61	123
evic_idx[2]	evic_op[1]	auto[1]	11	1		T216	1		T203	2		T272	1
evic_idx[2]	evic_op[1]	auto[2]	10	1		T345	1		T351	2		T344	5
evic_idx[2]	evic_op[1]	auto[3]	43	1		T216	3		T213	3		T203	1
evic_idx[2]	evic_op[2]	auto[0]	64	1		T23	1		T224	1		T214	9
evic_idx[2]	evic_op[2]	auto[1]	6	1		T84	2		T352	1		T346	1
evic_idx[2]	evic_op[2]	auto[3]	14	1		T62	1		T199	1		T200	1
evic_idx[3]	evic_op[1]	auto[0]	7687	1		T4	156		T6	66		T61	123
evic_idx[3]	evic_op[1]	auto[1]	11	1		T216	2		T203	1		T272	2
evic_idx[3]	evic_op[1]	auto[2]	9	1		T345	1		T351	1		T344	6
evic_idx[3]	evic_op[1]	auto[3]	45	1		T216	3		T213	2		T203	1
evic_idx[3]	evic_op[2]	auto[0]	61	1		T23	1		T224	1		T214	9
evic_idx[3]	evic_op[2]	auto[1]	7	1		T84	1		T352	1		T266	1
evic_idx[3]	evic_op[2]	auto[2]	2	1		T343	1		T353	1		-	-
evic_idx[3]	evic_op[2]	auto[3]	17	1		T62	1		T273	1		T354	1