Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	46199	1		T92	14163		T326	15081		T327	2313
rd_lvl[2]	46921	1		T92	10318		T93	13024		T326	10551
rd_lvl[3]	14419	1		T49	4373		T328	1252		T91	4798
rd_lvl[4]	44127	1		T37	4927		T49	3992		T105	4993
rd_lvl[5]	13692	1		T37	1241		T105	1099		T329	1010
rd_lvl[6]	16215	1		T330	2312		T331	899		T91	1
rd_lvl[7]	12709	1		T2	139		T330	818		T332	1745
rd_lvl[8]	6725	1		T2	38		T332	1331		T333	1325
rd_lvl[9]	2032	1		T2	3		T215	625		T334	620
rd_lvl[10]	4992	1		T2	2		T215	860		T335	1343
rd_lvl[11]	3027	1		T335	318		T267	326		T261	367
rd_lvl[12]	7475	1		T261	1116		T336	1339		T337	443
rd_lvl[13]	4438	1		T26	257		T337	1184		T338	518
rd_lvl[14]	8735	1		T26	1382		T35	263		T339	660
rd_lvl[15]	3563	1		T35	181		T339	120		T36	562