Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	372045	1		T1	1		T2	272		T3	1
all_pins[1]	372045	1		T1	1		T2	272		T3	1
all_pins[2]	372045	1		T1	1		T2	272		T3	1
all_pins[3]	372045	1		T1	1		T2	272		T3	1
all_pins[4]	372045	1		T1	1		T2	272		T3	1
all_pins[5]	372045	1		T1	1		T2	272		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1872604	1		T1	6		T2	1359		T3	6
values[0x1]	359666	1		T2	273		T29	1558		T31	1592
transitions[0x0=>0x1]	326260	1		T2	271		T29	1558		T31	1592
transitions[0x1=>0x0]	326242	1		T2	271		T29	1558		T31	1592

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	371894	1		T1	1		T2	272		T3	1
all_pins[0]	values[0x1]	151	1		T251	4		T252	3		T318	1
all_pins[0]	transitions[0x0=>0x1]	68	1		T251	3		T318	1		T319	1
all_pins[0]	transitions[0x1=>0x0]	79	1		T251	1		T252	3		T318	1
all_pins[1]	values[0x0]	371883	1		T1	1		T2	272		T3	1
all_pins[1]	values[0x1]	162	1		T251	2		T252	6		T318	1
all_pins[1]	transitions[0x0=>0x1]	129	1		T251	2		T252	3		T318	1
all_pins[1]	transitions[0x1=>0x0]	3275	1		T35	128		T36	939		T355	259
all_pins[2]	values[0x0]	368737	1		T1	1		T2	272		T3	1
all_pins[2]	values[0x1]	3308	1		T35	128		T36	939		T355	259
all_pins[2]	transitions[0x0=>0x1]	47	1		T252	3		T319	1		T320	1
all_pins[2]	transitions[0x1=>0x0]	235324	1		T2	182		T37	6168		T26	1639
all_pins[3]	values[0x0]	133460	1		T1	1		T2	90		T3	1
all_pins[3]	values[0x1]	238585	1		T2	182		T37	6168		T26	1639
all_pins[3]	transitions[0x0=>0x1]	208608	1		T2	180		T37	4626		T26	1639
all_pins[3]	transitions[0x1=>0x0]	87419	1		T2	89		T29	1558		T31	1592
all_pins[4]	values[0x0]	254649	1		T1	1		T2	181		T3	1
all_pins[4]	values[0x1]	117396	1		T2	91		T29	1558		T31	1592
all_pins[4]	transitions[0x0=>0x1]	117379	1		T2	91		T29	1558		T31	1592
all_pins[4]	transitions[0x1=>0x0]	47	1		T251	2		T252	1		T319	2
all_pins[5]	values[0x0]	371981	1		T1	1		T2	272		T3	1
all_pins[5]	values[0x1]	64	1		T251	2		T252	1		T319	3
all_pins[5]	transitions[0x0=>0x1]	29	1		T251	1		T322	1		T320	1
all_pins[5]	transitions[0x1=>0x0]	98	1		T251	3		T252	2		T318	1