Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	272	1		T251	4		T252	7		T318	7
all_values[1]	272	1		T251	4		T252	7		T318	7
all_values[2]	272	1		T251	4		T252	7		T318	7
all_values[3]	272	1		T251	4		T252	7		T318	7
all_values[4]	272	1		T251	4		T252	7		T318	7
all_values[5]	272	1		T251	4		T252	7		T318	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	914	1		T251	14		T252	23		T318	35
auto[1]	718	1		T251	10		T252	19		T318	7

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	523	1		T251	9		T252	13		T318	13
auto[1]	1109	1		T251	15		T252	29		T318	29

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	978	1		T251	16		T252	25		T318	22
auto[1]	654	1		T251	8		T252	17		T318	20

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	91	1		T252	2		T318	3		T319	3
all_values[0]	auto[0]	auto[1]	auto[1]	71	1		T251	2		T252	2		T319	1
all_values[0]	auto[1]	auto[0]	auto[1]	69	1		T251	1		T252	2		T318	4
all_values[0]	auto[1]	auto[1]	auto[1]	41	1		T251	1		T252	1		T319	2
all_values[1]	auto[0]	auto[0]	auto[1]	91	1		T251	2		T318	3		T319	2
all_values[1]	auto[0]	auto[1]	auto[1]	78	1		T251	2		T252	5		T318	1
all_values[1]	auto[1]	auto[0]	auto[1]	45	1		T252	1		T318	3		T320	3
all_values[1]	auto[1]	auto[1]	auto[1]	58	1		T252	1		T319	5		T320	2
all_values[2]	auto[0]	auto[0]	auto[0]	89	1		T251	3		T252	1		T318	2
all_values[2]	auto[0]	auto[1]	auto[0]	73	1		T251	1		T252	2		T318	1
all_values[2]	auto[1]	auto[0]	auto[1]	54	1		T318	4		T320	1		T321	1
all_values[2]	auto[1]	auto[1]	auto[1]	56	1		T252	4		T319	1		T322	1
all_values[3]	auto[0]	auto[0]	auto[0]	93	1		T251	2		T252	4		T318	2
all_values[3]	auto[0]	auto[1]	auto[0]	78	1		T319	3		T322	1		T320	3
all_values[3]	auto[1]	auto[0]	auto[1]	61	1		T251	2		T252	3		T318	4
all_values[3]	auto[1]	auto[1]	auto[1]	40	1		T318	1		T319	1		T322	1
all_values[4]	auto[0]	auto[0]	auto[0]	58	1		T251	1		T318	4		T319	1
all_values[4]	auto[0]	auto[0]	auto[1]	33	1		T252	2		T319	3		T322	1
all_values[4]	auto[0]	auto[1]	auto[0]	45	1		T251	2		T252	1		T319	1
all_values[4]	auto[0]	auto[1]	auto[1]	25	1		T318	2		T320	2		T323	1
all_values[4]	auto[1]	auto[0]	auto[1]	66	1		T251	1		T252	3		T318	1
all_values[4]	auto[1]	auto[1]	auto[1]	45	1		T252	1		T319	2		T322	1
all_values[5]	auto[0]	auto[0]	auto[0]	55	1		T252	4		T318	2		T319	1
all_values[5]	auto[0]	auto[0]	auto[1]	37	1		T251	1		T324	1		T325	1
all_values[5]	auto[0]	auto[1]	auto[0]	32	1		T252	1		T318	2		T319	2
all_values[5]	auto[0]	auto[1]	auto[1]	29	1		T252	1		T319	1		T322	1
all_values[5]	auto[1]	auto[0]	auto[1]	72	1		T251	1		T252	1		T318	3
all_values[5]	auto[1]	auto[1]	auto[1]	47	1		T251	2		T319	2		T322	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal