| T1070 |
/workspace/coverage/default/12.flash_ctrl_invalid_op.772004689 |
|
|
Jul 05 06:13:07 PM PDT 24 |
Jul 05 06:14:29 PM PDT 24 |
13883031100 ps |
| T1071 |
/workspace/coverage/default/41.flash_ctrl_hw_sec_otp.3667708552 |
|
|
Jul 05 06:15:54 PM PDT 24 |
Jul 05 06:16:57 PM PDT 24 |
2699769100 ps |
| T1072 |
/workspace/coverage/default/16.flash_ctrl_lcmgr_intg.4237792129 |
|
|
Jul 05 06:14:00 PM PDT 24 |
Jul 05 06:14:14 PM PDT 24 |
53287700 ps |
| T376 |
/workspace/coverage/default/5.flash_ctrl_disable.4155796292 |
|
|
Jul 05 06:12:00 PM PDT 24 |
Jul 05 06:12:23 PM PDT 24 |
10610600 ps |
| T1073 |
/workspace/coverage/default/5.flash_ctrl_invalid_op.1596404310 |
|
|
Jul 05 06:11:48 PM PDT 24 |
Jul 05 06:13:13 PM PDT 24 |
4590023200 ps |
| T1074 |
/workspace/coverage/default/13.flash_ctrl_prog_reset.3810186352 |
|
|
Jul 05 06:13:21 PM PDT 24 |
Jul 05 06:13:36 PM PDT 24 |
98673600 ps |
| T1075 |
/workspace/coverage/default/11.flash_ctrl_sec_info_access.3615687308 |
|
|
Jul 05 06:13:00 PM PDT 24 |
Jul 05 06:14:11 PM PDT 24 |
2107327900 ps |
| T1076 |
/workspace/coverage/default/1.flash_ctrl_read_word_sweep_derr.2120734913 |
|
|
Jul 05 06:10:51 PM PDT 24 |
Jul 05 06:11:15 PM PDT 24 |
20228200 ps |
| T1077 |
/workspace/coverage/default/9.flash_ctrl_mp_regions.2751072772 |
|
|
Jul 05 06:12:36 PM PDT 24 |
Jul 05 06:29:19 PM PDT 24 |
65843557900 ps |
| T1078 |
/workspace/coverage/default/12.flash_ctrl_lcmgr_intg.1278510677 |
|
|
Jul 05 06:13:08 PM PDT 24 |
Jul 05 06:13:23 PM PDT 24 |
15614900 ps |
| T1079 |
/workspace/coverage/default/16.flash_ctrl_otp_reset.4075581462 |
|
|
Jul 05 06:13:47 PM PDT 24 |
Jul 05 06:15:37 PM PDT 24 |
162614800 ps |
| T1080 |
/workspace/coverage/default/5.flash_ctrl_lcmgr_intg.3494124048 |
|
|
Jul 05 06:11:56 PM PDT 24 |
Jul 05 06:12:10 PM PDT 24 |
15832900 ps |
| T1081 |
/workspace/coverage/default/16.flash_ctrl_connect.3847960157 |
|
|
Jul 05 06:13:52 PM PDT 24 |
Jul 05 06:14:07 PM PDT 24 |
30573400 ps |
| T1082 |
/workspace/coverage/default/15.flash_ctrl_lcmgr_intg.2883107500 |
|
|
Jul 05 06:13:42 PM PDT 24 |
Jul 05 06:13:56 PM PDT 24 |
46487200 ps |
| T1083 |
/workspace/coverage/default/8.flash_ctrl_prog_reset.3718719987 |
|
|
Jul 05 06:12:28 PM PDT 24 |
Jul 05 06:12:45 PM PDT 24 |
156069600 ps |
| T1084 |
/workspace/coverage/default/27.flash_ctrl_otp_reset.2458392448 |
|
|
Jul 05 06:14:55 PM PDT 24 |
Jul 05 06:17:10 PM PDT 24 |
40159300 ps |
| T1085 |
/workspace/coverage/default/10.flash_ctrl_ro.3621291590 |
|
|
Jul 05 06:12:42 PM PDT 24 |
Jul 05 06:14:36 PM PDT 24 |
567027700 ps |
| T1086 |
/workspace/coverage/default/4.flash_ctrl_ro_serr.231829370 |
|
|
Jul 05 06:11:34 PM PDT 24 |
Jul 05 06:13:53 PM PDT 24 |
1431009900 ps |
| T1087 |
/workspace/coverage/default/0.flash_ctrl_fs_sup.1885588404 |
|
|
Jul 05 06:10:43 PM PDT 24 |
Jul 05 06:11:20 PM PDT 24 |
1648047200 ps |
| T1088 |
/workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.3235990525 |
|
|
Jul 05 06:14:08 PM PDT 24 |
Jul 05 06:15:40 PM PDT 24 |
10018291100 ps |
| T1089 |
/workspace/coverage/default/21.flash_ctrl_alert_test.1887538015 |
|
|
Jul 05 06:14:34 PM PDT 24 |
Jul 05 06:14:49 PM PDT 24 |
272506200 ps |
| T1090 |
/workspace/coverage/default/2.flash_ctrl_error_prog_type.2655234788 |
|
|
Jul 05 06:11:02 PM PDT 24 |
Jul 05 06:54:22 PM PDT 24 |
3582877400 ps |
| T1091 |
/workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.1834973839 |
|
|
Jul 05 06:12:21 PM PDT 24 |
Jul 05 06:14:05 PM PDT 24 |
10017981400 ps |
| T1092 |
/workspace/coverage/default/3.flash_ctrl_smoke.3210424449 |
|
|
Jul 05 06:11:13 PM PDT 24 |
Jul 05 06:12:29 PM PDT 24 |
17885000 ps |
| T1093 |
/workspace/coverage/default/3.flash_ctrl_intr_wr.1503621969 |
|
|
Jul 05 06:11:22 PM PDT 24 |
Jul 05 06:12:36 PM PDT 24 |
2993707500 ps |
| T1094 |
/workspace/coverage/default/0.flash_ctrl_connect.2007027663 |
|
|
Jul 05 06:10:43 PM PDT 24 |
Jul 05 06:10:57 PM PDT 24 |
30224400 ps |
| T1095 |
/workspace/coverage/default/33.flash_ctrl_otp_reset.491718821 |
|
|
Jul 05 06:15:17 PM PDT 24 |
Jul 05 06:17:29 PM PDT 24 |
305046300 ps |
| T1096 |
/workspace/coverage/default/11.flash_ctrl_rw_evict.1054620123 |
|
|
Jul 05 06:13:00 PM PDT 24 |
Jul 05 06:13:32 PM PDT 24 |
69738100 ps |
| T1097 |
/workspace/coverage/default/19.flash_ctrl_rw_evict_all_en.892370138 |
|
|
Jul 05 06:14:19 PM PDT 24 |
Jul 05 06:14:51 PM PDT 24 |
40471800 ps |
| T1098 |
/workspace/coverage/default/32.flash_ctrl_smoke.3878290282 |
|
|
Jul 05 06:15:14 PM PDT 24 |
Jul 05 06:17:16 PM PDT 24 |
117655100 ps |
| T1099 |
/workspace/coverage/default/47.flash_ctrl_otp_reset.3523297731 |
|
|
Jul 05 06:16:09 PM PDT 24 |
Jul 05 06:18:00 PM PDT 24 |
73617700 ps |
| T1100 |
/workspace/coverage/default/12.flash_ctrl_intr_rd.1433346686 |
|
|
Jul 05 06:13:07 PM PDT 24 |
Jul 05 06:15:15 PM PDT 24 |
691972200 ps |
| T1101 |
/workspace/coverage/default/4.flash_ctrl_fetch_code.687231679 |
|
|
Jul 05 06:11:34 PM PDT 24 |
Jul 05 06:12:00 PM PDT 24 |
1349344200 ps |
| T1102 |
/workspace/coverage/default/4.flash_ctrl_intr_wr.3756595148 |
|
|
Jul 05 06:11:51 PM PDT 24 |
Jul 05 06:13:03 PM PDT 24 |
3942987800 ps |
| T1103 |
/workspace/coverage/default/34.flash_ctrl_disable.1634248059 |
|
|
Jul 05 06:15:30 PM PDT 24 |
Jul 05 06:15:52 PM PDT 24 |
26302000 ps |
| T1104 |
/workspace/coverage/default/45.flash_ctrl_otp_reset.468145372 |
|
|
Jul 05 06:15:58 PM PDT 24 |
Jul 05 06:18:10 PM PDT 24 |
139089100 ps |
| T1105 |
/workspace/coverage/default/43.flash_ctrl_alert_test.1539119535 |
|
|
Jul 05 06:16:09 PM PDT 24 |
Jul 05 06:16:24 PM PDT 24 |
167527300 ps |
| T1106 |
/workspace/coverage/default/28.flash_ctrl_disable.2936320669 |
|
|
Jul 05 06:15:05 PM PDT 24 |
Jul 05 06:15:28 PM PDT 24 |
39618600 ps |
| T1107 |
/workspace/coverage/default/35.flash_ctrl_rw_evict_all_en.1939088189 |
|
|
Jul 05 06:15:31 PM PDT 24 |
Jul 05 06:16:02 PM PDT 24 |
42877900 ps |
| T1108 |
/workspace/coverage/default/22.flash_ctrl_intr_rd_slow_flash.2282425204 |
|
|
Jul 05 06:14:34 PM PDT 24 |
Jul 05 06:17:11 PM PDT 24 |
27207811900 ps |
| T1109 |
/workspace/coverage/default/3.flash_ctrl_full_mem_access.2771552980 |
|
|
Jul 05 06:11:13 PM PDT 24 |
Jul 05 06:55:57 PM PDT 24 |
159689364200 ps |
| T1110 |
/workspace/coverage/default/15.flash_ctrl_hw_sec_otp.1517666482 |
|
|
Jul 05 06:13:24 PM PDT 24 |
Jul 05 06:14:47 PM PDT 24 |
10522560500 ps |
| T251 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.1407092706 |
|
|
Jul 05 04:31:33 PM PDT 24 |
Jul 05 04:31:47 PM PDT 24 |
83438800 ps |
| T70 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3413968535 |
|
|
Jul 05 04:31:05 PM PDT 24 |
Jul 05 04:31:54 PM PDT 24 |
158555800 ps |
| T1111 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.3052676366 |
|
|
Jul 05 04:31:04 PM PDT 24 |
Jul 05 04:31:22 PM PDT 24 |
14625700 ps |
| T71 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.778872778 |
|
|
Jul 05 04:31:14 PM PDT 24 |
Jul 05 04:31:34 PM PDT 24 |
61393500 ps |
| T236 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.2863863938 |
|
|
Jul 05 04:31:04 PM PDT 24 |
Jul 05 04:31:21 PM PDT 24 |
18240500 ps |
| T111 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1047155934 |
|
|
Jul 05 04:31:05 PM PDT 24 |
Jul 05 04:31:27 PM PDT 24 |
99199800 ps |
| T72 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1586876599 |
|
|
Jul 05 04:31:14 PM PDT 24 |
Jul 05 04:31:52 PM PDT 24 |
3366479200 ps |
| T194 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.89200359 |
|
|
Jul 05 04:31:16 PM PDT 24 |
Jul 05 04:31:31 PM PDT 24 |
40741800 ps |
| T112 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.2886543343 |
|
|
Jul 05 04:31:10 PM PDT 24 |
Jul 05 04:39:02 PM PDT 24 |
4909897800 ps |
| T247 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2274757575 |
|
|
Jul 05 04:31:06 PM PDT 24 |
Jul 05 04:32:14 PM PDT 24 |
6456573900 ps |
| T1112 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1604660810 |
|
|
Jul 05 04:31:02 PM PDT 24 |
Jul 05 04:31:16 PM PDT 24 |
16249200 ps |
| T252 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.3784926221 |
|
|
Jul 05 04:31:05 PM PDT 24 |
Jul 05 04:31:20 PM PDT 24 |
31538100 ps |
| T237 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.696295531 |
|
|
Jul 05 04:31:07 PM PDT 24 |
Jul 05 04:31:23 PM PDT 24 |
34549900 ps |
| T1113 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.1920695184 |
|
|
Jul 05 04:31:06 PM PDT 24 |
Jul 05 04:31:25 PM PDT 24 |
42596300 ps |
| T248 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2883214184 |
|
|
Jul 05 04:31:36 PM PDT 24 |
Jul 05 04:31:51 PM PDT 24 |
114304000 ps |
| T250 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3718171460 |
|
|
Jul 05 04:31:10 PM PDT 24 |
Jul 05 04:31:26 PM PDT 24 |
93904600 ps |
| T1114 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1781797545 |
|
|
Jul 05 04:31:27 PM PDT 24 |
Jul 05 04:31:42 PM PDT 24 |
12162900 ps |
| T1115 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1230203881 |
|
|
Jul 05 04:31:16 PM PDT 24 |
Jul 05 04:31:30 PM PDT 24 |
33515700 ps |
| T1116 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.2808283252 |
|
|
Jul 05 04:31:31 PM PDT 24 |
Jul 05 04:31:45 PM PDT 24 |
24653900 ps |
| T318 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.1596808869 |
|
|
Jul 05 04:31:47 PM PDT 24 |
Jul 05 04:32:01 PM PDT 24 |
15163200 ps |
| T319 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.4022348008 |
|
|
Jul 05 04:31:43 PM PDT 24 |
Jul 05 04:31:57 PM PDT 24 |
30931800 ps |
| T238 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.4275442572 |
|
|
Jul 05 04:31:04 PM PDT 24 |
Jul 05 04:31:19 PM PDT 24 |
58698600 ps |
| T190 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.687817 |
|
|
Jul 05 04:31:27 PM PDT 24 |
Jul 05 04:31:43 PM PDT 24 |
56536800 ps |
| T1117 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1488091218 |
|
|
Jul 05 04:30:59 PM PDT 24 |
Jul 05 04:31:13 PM PDT 24 |
17327300 ps |
| T1118 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.3370164707 |
|
|
Jul 05 04:31:06 PM PDT 24 |
Jul 05 04:31:25 PM PDT 24 |
13432800 ps |
| T322 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.372477423 |
|
|
Jul 05 04:31:38 PM PDT 24 |
Jul 05 04:31:52 PM PDT 24 |
43354900 ps |
| T320 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.50786454 |
|
|
Jul 05 04:31:37 PM PDT 24 |
Jul 05 04:31:52 PM PDT 24 |
54501600 ps |
| T1119 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.3434633096 |
|
|
Jul 05 04:31:31 PM PDT 24 |
Jul 05 04:31:48 PM PDT 24 |
12771000 ps |
| T113 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.4227201069 |
|
|
Jul 05 04:31:27 PM PDT 24 |
Jul 05 04:31:47 PM PDT 24 |
30449900 ps |
| T191 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3971603173 |
|
|
Jul 05 04:31:14 PM PDT 24 |
Jul 05 04:31:32 PM PDT 24 |
284541100 ps |
| T192 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.3806581946 |
|
|
Jul 05 04:31:16 PM PDT 24 |
Jul 05 04:31:37 PM PDT 24 |
120098100 ps |
| T249 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.4109632099 |
|
|
Jul 05 04:31:27 PM PDT 24 |
Jul 05 04:31:45 PM PDT 24 |
303274000 ps |
| T371 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.451789872 |
|
|
Jul 05 04:31:05 PM PDT 24 |
Jul 05 04:32:11 PM PDT 24 |
4910585800 ps |
| T193 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.3179696079 |
|
|
Jul 05 04:31:28 PM PDT 24 |
Jul 05 04:37:57 PM PDT 24 |
436837400 ps |
| T246 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.1317586273 |
|
|
Jul 05 04:31:01 PM PDT 24 |
Jul 05 04:38:42 PM PDT 24 |
1387296600 ps |
| T283 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1733928436 |
|
|
Jul 05 04:31:08 PM PDT 24 |
Jul 05 04:31:27 PM PDT 24 |
40023500 ps |
| T232 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1172404451 |
|
|
Jul 05 04:31:09 PM PDT 24 |
Jul 05 04:31:27 PM PDT 24 |
127486700 ps |
| T321 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.4268339230 |
|
|
Jul 05 04:31:05 PM PDT 24 |
Jul 05 04:31:21 PM PDT 24 |
31125200 ps |
| T1120 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2919395352 |
|
|
Jul 05 04:31:05 PM PDT 24 |
Jul 05 04:31:26 PM PDT 24 |
163963700 ps |
| T1121 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.829751301 |
|
|
Jul 05 04:31:11 PM PDT 24 |
Jul 05 04:31:25 PM PDT 24 |
11224500 ps |
| T1122 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3804784618 |
|
|
Jul 05 04:31:10 PM PDT 24 |
Jul 05 04:31:27 PM PDT 24 |
19389800 ps |
| T233 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2137948282 |
|
|
Jul 05 04:31:13 PM PDT 24 |
Jul 05 04:31:30 PM PDT 24 |
62536800 ps |
| T1123 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3444673587 |
|
|
Jul 05 04:31:24 PM PDT 24 |
Jul 05 04:31:39 PM PDT 24 |
12252700 ps |
| T372 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3750490705 |
|
|
Jul 05 04:31:06 PM PDT 24 |
Jul 05 04:32:03 PM PDT 24 |
636466600 ps |
| T324 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.3931818290 |
|
|
Jul 05 04:31:24 PM PDT 24 |
Jul 05 04:31:38 PM PDT 24 |
15749000 ps |
| T234 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1323037766 |
|
|
Jul 05 04:31:51 PM PDT 24 |
Jul 05 04:32:11 PM PDT 24 |
113229100 ps |
| T235 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1103507044 |
|
|
Jul 05 04:31:21 PM PDT 24 |
Jul 05 04:31:42 PM PDT 24 |
63889100 ps |
| T1124 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.233822081 |
|
|
Jul 05 04:31:26 PM PDT 24 |
Jul 05 04:31:40 PM PDT 24 |
138785300 ps |
| T284 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3643195025 |
|
|
Jul 05 04:31:01 PM PDT 24 |
Jul 05 04:31:48 PM PDT 24 |
49013400 ps |
| T325 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.932571613 |
|
|
Jul 05 04:31:42 PM PDT 24 |
Jul 05 04:31:55 PM PDT 24 |
14628200 ps |
| T323 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.191778139 |
|
|
Jul 05 04:31:01 PM PDT 24 |
Jul 05 04:31:16 PM PDT 24 |
29878400 ps |
| T1125 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.2373480094 |
|
|
Jul 05 04:31:40 PM PDT 24 |
Jul 05 04:31:54 PM PDT 24 |
56092200 ps |
| T253 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.2735604119 |
|
|
Jul 05 04:31:20 PM PDT 24 |
Jul 05 04:31:40 PM PDT 24 |
193730000 ps |
| T1126 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.2133240167 |
|
|
Jul 05 04:31:42 PM PDT 24 |
Jul 05 04:31:57 PM PDT 24 |
15398600 ps |
| T1127 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.376864498 |
|
|
Jul 05 04:31:07 PM PDT 24 |
Jul 05 04:31:28 PM PDT 24 |
86727600 ps |
| T1128 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1808791034 |
|
|
Jul 05 04:31:34 PM PDT 24 |
Jul 05 04:31:51 PM PDT 24 |
20608400 ps |
| T1129 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.187015437 |
|
|
Jul 05 04:31:36 PM PDT 24 |
Jul 05 04:31:50 PM PDT 24 |
15202300 ps |
| T258 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.190975607 |
|
|
Jul 05 04:31:08 PM PDT 24 |
Jul 05 04:31:26 PM PDT 24 |
78112100 ps |
| T1130 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.4101089437 |
|
|
Jul 05 04:31:02 PM PDT 24 |
Jul 05 04:31:17 PM PDT 24 |
27326200 ps |
| T254 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.118467255 |
|
|
Jul 05 04:31:38 PM PDT 24 |
Jul 05 04:31:58 PM PDT 24 |
601212000 ps |
| T1131 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2271836043 |
|
|
Jul 05 04:31:03 PM PDT 24 |
Jul 05 04:31:21 PM PDT 24 |
127789200 ps |
| T1132 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.163324009 |
|
|
Jul 05 04:31:05 PM PDT 24 |
Jul 05 04:31:22 PM PDT 24 |
26799300 ps |
| T1133 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.47115805 |
|
|
Jul 05 04:31:12 PM PDT 24 |
Jul 05 04:31:29 PM PDT 24 |
207250600 ps |
| T1134 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.898433786 |
|
|
Jul 05 04:31:32 PM PDT 24 |
Jul 05 04:31:49 PM PDT 24 |
146208600 ps |
| T1135 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1122618068 |
|
|
Jul 05 04:31:06 PM PDT 24 |
Jul 05 04:32:23 PM PDT 24 |
6606376800 ps |
| T285 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.424010647 |
|
|
Jul 05 04:31:30 PM PDT 24 |
Jul 05 04:37:57 PM PDT 24 |
1577502400 ps |
| T1136 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.3915261552 |
|
|
Jul 05 04:31:43 PM PDT 24 |
Jul 05 04:31:57 PM PDT 24 |
26129700 ps |
| T286 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.1066776722 |
|
|
Jul 05 04:31:04 PM PDT 24 |
Jul 05 04:31:36 PM PDT 24 |
425014000 ps |
| T287 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.932919570 |
|
|
Jul 05 04:31:19 PM PDT 24 |
Jul 05 04:31:38 PM PDT 24 |
204084000 ps |
| T360 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.1136038521 |
|
|
Jul 05 04:31:29 PM PDT 24 |
Jul 05 04:46:30 PM PDT 24 |
359863200 ps |
| T1137 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.433216926 |
|
|
Jul 05 04:31:07 PM PDT 24 |
Jul 05 04:31:24 PM PDT 24 |
53123800 ps |
| T1138 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.909008998 |
|
|
Jul 05 04:31:10 PM PDT 24 |
Jul 05 04:31:26 PM PDT 24 |
15612500 ps |
| T1139 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.1470119042 |
|
|
Jul 05 04:31:30 PM PDT 24 |
Jul 05 04:31:47 PM PDT 24 |
40234800 ps |
| T1140 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.470711919 |
|
|
Jul 05 04:31:42 PM PDT 24 |
Jul 05 04:31:57 PM PDT 24 |
18284600 ps |
| T1141 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.493512657 |
|
|
Jul 05 04:31:36 PM PDT 24 |
Jul 05 04:31:56 PM PDT 24 |
57362300 ps |
| T1142 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.702757466 |
|
|
Jul 05 04:31:19 PM PDT 24 |
Jul 05 04:31:41 PM PDT 24 |
51273600 ps |
| T1143 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.1749208327 |
|
|
Jul 05 04:31:22 PM PDT 24 |
Jul 05 04:31:38 PM PDT 24 |
12369300 ps |
| T1144 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.1425563595 |
|
|
Jul 05 04:31:16 PM PDT 24 |
Jul 05 04:31:30 PM PDT 24 |
25615900 ps |
| T1145 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3498958690 |
|
|
Jul 05 04:31:06 PM PDT 24 |
Jul 05 04:31:34 PM PDT 24 |
19475400 ps |
| T1146 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.2727384549 |
|
|
Jul 05 04:31:40 PM PDT 24 |
Jul 05 04:31:54 PM PDT 24 |
27992400 ps |
| T1147 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.1305572883 |
|
|
Jul 05 04:31:44 PM PDT 24 |
Jul 05 04:31:58 PM PDT 24 |
25922900 ps |
| T1148 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2950851220 |
|
|
Jul 05 04:31:31 PM PDT 24 |
Jul 05 04:31:48 PM PDT 24 |
30549500 ps |
| T255 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.2278939959 |
|
|
Jul 05 04:31:04 PM PDT 24 |
Jul 05 04:31:25 PM PDT 24 |
199159900 ps |
| T1149 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1108849930 |
|
|
Jul 05 04:31:08 PM PDT 24 |
Jul 05 04:31:23 PM PDT 24 |
12081900 ps |
| T1150 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2078155909 |
|
|
Jul 05 04:31:28 PM PDT 24 |
Jul 05 04:32:03 PM PDT 24 |
114427600 ps |
| T289 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.2868241168 |
|
|
Jul 05 04:31:03 PM PDT 24 |
Jul 05 04:31:21 PM PDT 24 |
83072900 ps |
| T1151 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.2612102073 |
|
|
Jul 05 04:31:10 PM PDT 24 |
Jul 05 04:31:25 PM PDT 24 |
16508000 ps |
| T1152 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.1603293353 |
|
|
Jul 05 04:31:15 PM PDT 24 |
Jul 05 04:31:29 PM PDT 24 |
25443700 ps |
| T288 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.935195585 |
|
|
Jul 05 04:31:00 PM PDT 24 |
Jul 05 04:31:20 PM PDT 24 |
336971800 ps |
| T1153 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1575482153 |
|
|
Jul 05 04:31:39 PM PDT 24 |
Jul 05 04:31:53 PM PDT 24 |
16133800 ps |
| T256 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1217330487 |
|
|
Jul 05 04:31:15 PM PDT 24 |
Jul 05 04:46:21 PM PDT 24 |
3922836300 ps |
| T361 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.68991718 |
|
|
Jul 05 04:31:07 PM PDT 24 |
Jul 05 04:38:47 PM PDT 24 |
364007600 ps |
| T357 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3467358079 |
|
|
Jul 05 04:31:28 PM PDT 24 |
Jul 05 04:46:27 PM PDT 24 |
686879400 ps |
| T1154 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2456123960 |
|
|
Jul 05 04:31:44 PM PDT 24 |
Jul 05 04:32:03 PM PDT 24 |
29122200 ps |
| T1155 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.4099386060 |
|
|
Jul 05 04:31:50 PM PDT 24 |
Jul 05 04:32:05 PM PDT 24 |
15463800 ps |
| T1156 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.629852604 |
|
|
Jul 05 04:31:06 PM PDT 24 |
Jul 05 04:31:22 PM PDT 24 |
36797700 ps |
| T1157 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3130465100 |
|
|
Jul 05 04:31:50 PM PDT 24 |
Jul 05 04:32:06 PM PDT 24 |
12500800 ps |
| T290 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.3294729820 |
|
|
Jul 05 04:31:07 PM PDT 24 |
Jul 05 04:31:28 PM PDT 24 |
222728800 ps |
| T291 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2757806561 |
|
|
Jul 05 04:31:32 PM PDT 24 |
Jul 05 04:31:53 PM PDT 24 |
499990400 ps |
| T1158 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.3317611580 |
|
|
Jul 05 04:31:41 PM PDT 24 |
Jul 05 04:31:55 PM PDT 24 |
42428500 ps |
| T1159 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.3268440740 |
|
|
Jul 05 04:31:14 PM PDT 24 |
Jul 05 04:31:28 PM PDT 24 |
38654300 ps |
| T239 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.636735420 |
|
|
Jul 05 04:31:04 PM PDT 24 |
Jul 05 04:31:19 PM PDT 24 |
52041500 ps |
| T1160 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1760576547 |
|
|
Jul 05 04:31:13 PM PDT 24 |
Jul 05 04:31:32 PM PDT 24 |
433305700 ps |
| T1161 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.4290367273 |
|
|
Jul 05 04:31:09 PM PDT 24 |
Jul 05 04:31:26 PM PDT 24 |
44108600 ps |
| T1162 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.1962016107 |
|
|
Jul 05 04:31:03 PM PDT 24 |
Jul 05 04:31:24 PM PDT 24 |
153551300 ps |
| T1163 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.3481001628 |
|
|
Jul 05 04:31:09 PM PDT 24 |
Jul 05 04:31:27 PM PDT 24 |
22505100 ps |
| T1164 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.2250760745 |
|
|
Jul 05 04:31:08 PM PDT 24 |
Jul 05 04:31:23 PM PDT 24 |
15646300 ps |
| T1165 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.4143033344 |
|
|
Jul 05 04:30:55 PM PDT 24 |
Jul 05 04:31:52 PM PDT 24 |
659975600 ps |
| T1166 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.588240536 |
|
|
Jul 05 04:30:59 PM PDT 24 |
Jul 05 04:31:19 PM PDT 24 |
183892300 ps |
| T1167 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.4018457063 |
|
|
Jul 05 04:31:37 PM PDT 24 |
Jul 05 04:31:55 PM PDT 24 |
97953800 ps |
| T1168 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.1692768401 |
|
|
Jul 05 04:31:04 PM PDT 24 |
Jul 05 04:31:23 PM PDT 24 |
32789500 ps |
| T1169 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.1030171245 |
|
|
Jul 05 04:31:00 PM PDT 24 |
Jul 05 04:31:51 PM PDT 24 |
18215337500 ps |
| T1170 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.244825089 |
|
|
Jul 05 04:31:38 PM PDT 24 |
Jul 05 04:31:52 PM PDT 24 |
34991500 ps |
| T257 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.1905898351 |
|
|
Jul 05 04:31:04 PM PDT 24 |
Jul 05 04:31:25 PM PDT 24 |
59107100 ps |
| T1171 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.1890300791 |
|
|
Jul 05 04:31:44 PM PDT 24 |
Jul 05 04:31:58 PM PDT 24 |
30994500 ps |
| T1172 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.3868277883 |
|
|
Jul 05 04:31:10 PM PDT 24 |
Jul 05 04:31:29 PM PDT 24 |
65587500 ps |
| T1173 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.4233143853 |
|
|
Jul 05 04:31:30 PM PDT 24 |
Jul 05 04:31:47 PM PDT 24 |
34651500 ps |
| T1174 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2591119176 |
|
|
Jul 05 04:31:42 PM PDT 24 |
Jul 05 04:31:57 PM PDT 24 |
18049400 ps |
| T1175 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.3372230380 |
|
|
Jul 05 04:31:17 PM PDT 24 |
Jul 05 04:31:38 PM PDT 24 |
220995100 ps |
| T1176 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.3205552110 |
|
|
Jul 05 04:31:43 PM PDT 24 |
Jul 05 04:31:57 PM PDT 24 |
24559600 ps |
| T1177 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.2952606061 |
|
|
Jul 05 04:31:45 PM PDT 24 |
Jul 05 04:31:59 PM PDT 24 |
30154000 ps |
| T292 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.215804093 |
|
|
Jul 05 04:31:31 PM PDT 24 |
Jul 05 04:31:50 PM PDT 24 |
119892800 ps |
| T1178 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.3870115742 |
|
|
Jul 05 04:31:40 PM PDT 24 |
Jul 05 04:31:56 PM PDT 24 |
13659000 ps |
| T362 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.727314332 |
|
|
Jul 05 04:31:03 PM PDT 24 |
Jul 05 04:38:43 PM PDT 24 |
1461725500 ps |
| T1179 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.1082494162 |
|
|
Jul 05 04:31:33 PM PDT 24 |
Jul 05 04:31:51 PM PDT 24 |
41684800 ps |
| T1180 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.2572240315 |
|
|
Jul 05 04:31:26 PM PDT 24 |
Jul 05 04:31:43 PM PDT 24 |
43093200 ps |
| T1181 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.2423508359 |
|
|
Jul 05 04:31:15 PM PDT 24 |
Jul 05 04:31:31 PM PDT 24 |
21795900 ps |
| T365 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.4061536652 |
|
|
Jul 05 04:31:21 PM PDT 24 |
Jul 05 04:43:54 PM PDT 24 |
4435651800 ps |
| T1182 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3658875484 |
|
|
Jul 05 04:31:27 PM PDT 24 |
Jul 05 04:31:46 PM PDT 24 |
206682100 ps |
| T293 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.4184563875 |
|
|
Jul 05 04:31:38 PM PDT 24 |
Jul 05 04:32:15 PM PDT 24 |
215202800 ps |
| T294 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.117341258 |
|
|
Jul 05 04:31:18 PM PDT 24 |
Jul 05 04:31:40 PM PDT 24 |
416308500 ps |
| T1183 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2902713004 |
|
|
Jul 05 04:31:18 PM PDT 24 |
Jul 05 04:31:54 PM PDT 24 |
803375300 ps |
| T1184 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.3215584874 |
|
|
Jul 05 04:31:07 PM PDT 24 |
Jul 05 04:31:24 PM PDT 24 |
331910100 ps |
| T1185 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.2408347188 |
|
|
Jul 05 04:31:06 PM PDT 24 |
Jul 05 04:31:22 PM PDT 24 |
16911000 ps |
| T1186 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3942692636 |
|
|
Jul 05 04:31:05 PM PDT 24 |
Jul 05 04:31:21 PM PDT 24 |
48217400 ps |
| T1187 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.4044155396 |
|
|
Jul 05 04:31:00 PM PDT 24 |
Jul 05 04:31:17 PM PDT 24 |
14827600 ps |
| T1188 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.1056414732 |
|
|
Jul 05 04:31:43 PM PDT 24 |
Jul 05 04:32:00 PM PDT 24 |
88260300 ps |
| T1189 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.473681932 |
|
|
Jul 05 04:31:02 PM PDT 24 |
Jul 05 04:31:21 PM PDT 24 |
351208000 ps |
| T1190 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.2487075482 |
|
|
Jul 05 04:31:04 PM PDT 24 |
Jul 05 04:31:20 PM PDT 24 |
115666900 ps |
| T1191 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.3337653735 |
|
|
Jul 05 04:31:10 PM PDT 24 |
Jul 05 04:31:28 PM PDT 24 |
23137700 ps |
| T1192 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.68292726 |
|
|
Jul 05 04:31:09 PM PDT 24 |
Jul 05 04:31:24 PM PDT 24 |
41531300 ps |
| T1193 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2755037741 |
|
|
Jul 05 04:31:20 PM PDT 24 |
Jul 05 04:31:51 PM PDT 24 |
866320200 ps |
| T1194 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2503196927 |
|
|
Jul 05 04:31:05 PM PDT 24 |
Jul 05 04:31:27 PM PDT 24 |
197790500 ps |
| T1195 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.3579883692 |
|
|
Jul 05 04:31:38 PM PDT 24 |
Jul 05 04:31:57 PM PDT 24 |
88408200 ps |
| T1196 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.1131454919 |
|
|
Jul 05 04:31:36 PM PDT 24 |
Jul 05 04:31:50 PM PDT 24 |
54945200 ps |
| T1197 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.4137277936 |
|
|
Jul 05 04:31:07 PM PDT 24 |
Jul 05 04:31:40 PM PDT 24 |
36174400 ps |
| T1198 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2859333247 |
|
|
Jul 05 04:31:00 PM PDT 24 |
Jul 05 04:31:17 PM PDT 24 |
39950200 ps |
| T1199 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2695737304 |
|
|
Jul 05 04:31:04 PM PDT 24 |
Jul 05 04:31:45 PM PDT 24 |
168632900 ps |
| T364 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.3744930333 |
|
|
Jul 05 04:31:10 PM PDT 24 |
Jul 05 04:38:55 PM PDT 24 |
445710400 ps |
| T1200 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.835934541 |
|
|
Jul 05 04:31:27 PM PDT 24 |
Jul 05 04:31:43 PM PDT 24 |
16119900 ps |
| T1201 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3303493214 |
|
|
Jul 05 04:31:03 PM PDT 24 |
Jul 05 04:32:15 PM PDT 24 |
7270622400 ps |
| T1202 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.834837975 |
|
|
Jul 05 04:31:23 PM PDT 24 |
Jul 05 04:31:42 PM PDT 24 |
198217500 ps |
| T1203 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.2255837668 |
|
|
Jul 05 04:31:09 PM PDT 24 |
Jul 05 04:31:28 PM PDT 24 |
100525600 ps |
| T356 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.3549543017 |
|
|
Jul 05 04:31:09 PM PDT 24 |
Jul 05 04:31:29 PM PDT 24 |
187805000 ps |
| T1204 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1498666917 |
|
|
Jul 05 04:31:14 PM PDT 24 |
Jul 05 04:31:32 PM PDT 24 |
58345100 ps |
| T1205 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.2719062808 |
|
|
Jul 05 04:31:05 PM PDT 24 |
Jul 05 04:31:22 PM PDT 24 |
711232400 ps |
| T1206 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.4048817190 |
|
|
Jul 05 04:31:36 PM PDT 24 |
Jul 05 04:31:50 PM PDT 24 |
48462800 ps |
| T1207 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.2489718175 |
|
|
Jul 05 04:31:04 PM PDT 24 |
Jul 05 04:38:54 PM PDT 24 |
713043900 ps |
| T1208 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3336878432 |
|
|
Jul 05 04:31:32 PM PDT 24 |
Jul 05 04:31:47 PM PDT 24 |
14921400 ps |
| T1209 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.2221595777 |
|
|
Jul 05 04:31:23 PM PDT 24 |
Jul 05 04:31:39 PM PDT 24 |
100037400 ps |
| T1210 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.613552847 |
|
|
Jul 05 04:31:42 PM PDT 24 |
Jul 05 04:31:56 PM PDT 24 |
27471500 ps |
| T1211 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.2885609545 |
|
|
Jul 05 04:32:00 PM PDT 24 |
Jul 05 04:32:14 PM PDT 24 |
17402100 ps |
| T1212 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.634887469 |
|
|
Jul 05 04:31:14 PM PDT 24 |
Jul 05 04:31:31 PM PDT 24 |
237885700 ps |
| T1213 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2156221312 |
|
|
Jul 05 04:31:09 PM PDT 24 |
Jul 05 04:31:29 PM PDT 24 |
790289400 ps |
| T1214 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.889956627 |
|
|
Jul 05 04:31:35 PM PDT 24 |
Jul 05 04:31:53 PM PDT 24 |
189322100 ps |
| T1215 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.3958875782 |
|
|
Jul 05 04:31:21 PM PDT 24 |
Jul 05 04:31:35 PM PDT 24 |
25506300 ps |
| T1216 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.3597943937 |
|
|
Jul 05 04:31:51 PM PDT 24 |
Jul 05 04:32:04 PM PDT 24 |
26296600 ps |
| T1217 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.4114372876 |
|
|
Jul 05 04:31:46 PM PDT 24 |
Jul 05 04:32:03 PM PDT 24 |
24194000 ps |
| T1218 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.1139587478 |
|
|
Jul 05 04:30:57 PM PDT 24 |
Jul 05 04:31:12 PM PDT 24 |
39074200 ps |
| T240 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.4179165723 |
|
|
Jul 05 04:31:05 PM PDT 24 |
Jul 05 04:31:21 PM PDT 24 |
60945700 ps |
| T1219 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.397736651 |
|
|
Jul 05 04:31:46 PM PDT 24 |
Jul 05 04:32:00 PM PDT 24 |
50776400 ps |
| T1220 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.4021564213 |
|
|
Jul 05 04:31:14 PM PDT 24 |
Jul 05 04:31:33 PM PDT 24 |
421363900 ps |
| T1221 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2428903183 |
|
|
Jul 05 04:31:21 PM PDT 24 |
Jul 05 04:31:41 PM PDT 24 |
99991300 ps |
| T1222 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2402510171 |
|
|
Jul 05 04:32:12 PM PDT 24 |
Jul 05 04:32:26 PM PDT 24 |
74570000 ps |
| T1223 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.662247699 |
|
|
Jul 05 04:31:14 PM PDT 24 |
Jul 05 04:31:31 PM PDT 24 |
13132400 ps |
| T1224 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.1281191561 |
|
|
Jul 05 04:31:26 PM PDT 24 |
Jul 05 04:31:43 PM PDT 24 |
70201800 ps |
| T1225 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.2193920613 |
|
|
Jul 05 04:31:55 PM PDT 24 |
Jul 05 04:32:09 PM PDT 24 |
182194100 ps |
| T1226 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.2631983391 |
|
|
Jul 05 04:31:30 PM PDT 24 |
Jul 05 04:31:48 PM PDT 24 |
68300300 ps |
| T1227 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.1359240364 |
|
|
Jul 05 04:31:28 PM PDT 24 |
Jul 05 04:31:49 PM PDT 24 |
340239500 ps |
| T1228 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.3867124412 |
|
|
Jul 05 04:31:42 PM PDT 24 |
Jul 05 04:31:59 PM PDT 24 |
114725700 ps |
| T1229 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.2656668350 |
|
|
Jul 05 04:31:37 PM PDT 24 |
Jul 05 04:31:52 PM PDT 24 |
15863400 ps |
| T1230 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3778205159 |
|
|
Jul 05 04:31:35 PM PDT 24 |
Jul 05 04:31:52 PM PDT 24 |
36993800 ps |
| T1231 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.246811022 |
|
|
Jul 05 04:31:22 PM PDT 24 |
Jul 05 04:31:36 PM PDT 24 |
29798000 ps |
| T1232 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.2446525710 |
|
|
Jul 05 04:31:40 PM PDT 24 |
Jul 05 04:31:55 PM PDT 24 |
13971200 ps |
| T1233 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.199461251 |
|
|
Jul 05 04:31:47 PM PDT 24 |
Jul 05 04:32:05 PM PDT 24 |
85669000 ps |
| T1234 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3930324963 |
|
|
Jul 05 04:31:15 PM PDT 24 |
Jul 05 04:43:54 PM PDT 24 |
1744377200 ps |
| T1235 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2033596136 |
|
|
Jul 05 04:31:22 PM PDT 24 |
Jul 05 04:31:37 PM PDT 24 |
697285800 ps |
| T1236 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.640060904 |
|
|
Jul 05 04:31:05 PM PDT 24 |
Jul 05 04:31:23 PM PDT 24 |
13811400 ps |
| T1237 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.3885554283 |
|
|
Jul 05 04:31:12 PM PDT 24 |
Jul 05 04:31:26 PM PDT 24 |
26542300 ps |
| T1238 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.2320789888 |
|
|
Jul 05 04:31:37 PM PDT 24 |
Jul 05 04:31:51 PM PDT 24 |
49147000 ps |
| T1239 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.3976006854 |
|
|
Jul 05 04:31:05 PM PDT 24 |
Jul 05 04:31:23 PM PDT 24 |
36802900 ps |
| T1240 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2638005828 |
|
|
Jul 05 04:31:28 PM PDT 24 |
Jul 05 04:31:43 PM PDT 24 |
92401200 ps |
| T1241 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.1486062546 |
|
|
Jul 05 04:31:41 PM PDT 24 |
Jul 05 04:39:19 PM PDT 24 |
685779300 ps |
| T359 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1590867513 |
|
|
Jul 05 04:31:27 PM PDT 24 |
Jul 05 04:46:26 PM PDT 24 |
1371606400 ps |
| T366 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.972157759 |
|
|
Jul 05 04:31:04 PM PDT 24 |
Jul 05 04:38:48 PM PDT 24 |
2262780000 ps |
| T367 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.30753490 |
|
|
Jul 05 04:31:17 PM PDT 24 |
Jul 05 04:43:57 PM PDT 24 |
671516100 ps |
| T358 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.4022496674 |
|
|
Jul 05 04:31:31 PM PDT 24 |
Jul 05 04:46:36 PM PDT 24 |
3212360500 ps |
| T1242 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.995782388 |
|
|
Jul 05 04:31:11 PM PDT 24 |
Jul 05 04:31:29 PM PDT 24 |
48905700 ps |
| T1243 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.4071293834 |
|
|
Jul 05 04:31:37 PM PDT 24 |
Jul 05 04:31:51 PM PDT 24 |
54650900 ps |
| T1244 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1209651134 |
|
|
Jul 05 04:31:10 PM PDT 24 |
Jul 05 04:31:32 PM PDT 24 |
58732700 ps |
| T1245 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3765220452 |
|
|
Jul 05 04:31:01 PM PDT 24 |
Jul 05 04:31:21 PM PDT 24 |
84791400 ps |
| T1246 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2726617599 |
|
|
Jul 05 04:31:33 PM PDT 24 |
Jul 05 04:31:50 PM PDT 24 |
41111000 ps |
| T368 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3698881999 |
|
|
Jul 05 04:31:18 PM PDT 24 |
Jul 05 04:38:56 PM PDT 24 |
627849700 ps |
| T1247 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.43218711 |
|
|
Jul 05 04:31:14 PM PDT 24 |
Jul 05 04:31:34 PM PDT 24 |
106408800 ps |
| T1248 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.3404376476 |
|
|
Jul 05 04:31:32 PM PDT 24 |
Jul 05 04:31:46 PM PDT 24 |
53832400 ps |
| T363 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2173908383 |
|
|
Jul 05 04:31:09 PM PDT 24 |
Jul 05 04:46:21 PM PDT 24 |
2414664100 ps |
| T1249 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.3345143845 |
|
|
Jul 05 04:31:50 PM PDT 24 |
Jul 05 04:32:05 PM PDT 24 |
54049100 ps |
| T1250 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.626788620 |
|
|
Jul 05 04:31:06 PM PDT 24 |
Jul 05 04:31:25 PM PDT 24 |
36268400 ps |