Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	317299	1		T1	2		T3	2		T4	2
all_values[1]	317299	1		T1	2		T3	2		T4	2
all_values[2]	317299	1		T1	2		T3	2		T4	2
all_values[3]	317299	1		T1	2		T3	2		T4	2
all_values[4]	317299	1		T1	2		T3	2		T4	2
all_values[5]	317299	1		T1	2		T3	2		T4	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	640840	1		T1	12		T3	12		T4	12
auto[1]	1262954	1		T29	21576		T39	5124		T36	13048

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	926193	1		T1	7		T3	7		T4	7
auto[1]	977601	1		T1	5		T3	5		T4	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	317126	1		T1	2		T3	2		T4	2
all_values[0]	auto[1]	auto[1]	173	1		T263	1		T264	1		T265	5
all_values[1]	auto[0]	auto[1]	317127	1		T1	2		T3	2		T4	2
all_values[1]	auto[1]	auto[1]	172	1		T263	2		T264	7		T265	4
all_values[2]	auto[0]	auto[0]	1589	1		T1	2		T3	2		T4	2
all_values[2]	auto[0]	auto[1]	40	1		T263	1		T265	3		T316	1
all_values[2]	auto[1]	auto[0]	315601	1		T29	5394		T39	1281		T36	3262
all_values[2]	auto[1]	auto[1]	69	1		T264	2		T316	3		T317	1
all_values[3]	auto[0]	auto[0]	1581	1		T1	2		T3	2		T4	2
all_values[3]	auto[0]	auto[1]	61	1		T263	2		T264	2		T265	2
all_values[3]	auto[1]	auto[0]	70571	1		T29	594		T39	296		T36	1631
all_values[3]	auto[1]	auto[1]	245086	1		T29	4800		T39	985		T36	1631
all_values[4]	auto[0]	auto[0]	1125	1		T1	1		T3	1		T4	1
all_values[4]	auto[0]	auto[1]	542	1		T1	1		T3	1		T4	1
all_values[4]	auto[1]	auto[0]	218600	1		T29	3794		T39	946		T36	1631
all_values[4]	auto[1]	auto[1]	97032	1		T29	1600		T39	335		T36	1631
all_values[5]	auto[0]	auto[0]	1535	1		T1	2		T3	2		T4	2
all_values[5]	auto[0]	auto[1]	114	1		T42	1		T43	1		T44	1
all_values[5]	auto[1]	auto[0]	315591	1		T29	5394		T39	1281		T36	3262
all_values[5]	auto[1]	auto[1]	59	1		T264	2		T265	2		T317	2