Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	242645	1		T1	309		T3	40		T4	600
auto[FlashEraseBank]	270527	1		T3	19		T5	777		T6	3

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	256473	1		T1	9		T3	26		T4	200
auto[FlashOpProgram]	237639	1		T1	288		T3	31		T4	100
auto[FlashOpErase]	15060	1		T1	12		T3	2		T4	100
auto[FlashOpInvalid]	4000	1		T4	200		T48	200		T151	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	256473	1		T1	9		T3	26		T4	200
op[FlashOpProgram]	237639	1		T1	288		T3	31		T4	100
op[FlashOpErase]	15060	1		T1	12		T3	2		T4	100
read_erase_read	556	1		T1	1		T6	1		T23	5
read_prog_read	860	1		T3	2		T6	1		T54	5

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	372521	1		T3	31		T4	588		T5	1113
auto[FlashPartInfo]	136814	1		T1	309		T3	13		T4	6
auto[FlashPartInfo1]	822	1		T3	11		T4	6		T5	2
auto[FlashPartInfo2]	3015	1		T3	4		T5	11		T54	18

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	183967	1		T3	10		T4	196		T5	1113
auto[FlashPartData]	auto[FlashOpProgram]	180983	1		T3	20		T4	98		T6	4
auto[FlashPartData]	auto[FlashOpErase]	3663	1		T3	1		T4	98		T6	5
auto[FlashPartData]	auto[FlashOpInvalid]	3908	1		T4	196		T48	200		T151	196
auto[FlashPartInfo]	auto[FlashOpRead]	69817	1		T1	9		T3	4		T4	2
auto[FlashPartInfo]	auto[FlashOpProgram]	55564	1		T1	288		T3	8		T4	1
auto[FlashPartInfo]	auto[FlashOpErase]	11363	1		T1	12		T3	1		T4	1
auto[FlashPartInfo]	auto[FlashOpInvalid]	70	1		T4	2		T151	4		T153	10
auto[FlashPartInfo1]	auto[FlashOpRead]	648	1		T3	11		T4	2		T5	2
auto[FlashPartInfo1]	auto[FlashOpProgram]	166	1		T4	1		T154	1		T138	1
auto[FlashPartInfo1]	auto[FlashOpErase]	4	1		T4	1		T154	1		T144	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T4	2		T154	2		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	2041	1		T3	1		T5	11		T54	6
auto[FlashPartInfo2]	auto[FlashOpProgram]	926	1		T3	3		T54	12		T58	7
auto[FlashPartInfo2]	auto[FlashOpErase]	30	1		T34	1		T49	1		T70	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	18	1		T159	2		T162	2		T411	2