Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.62	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	1	31	96.88

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	1	31	96.88	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29533	1		T4	400		T23	16		T34	16
auto[1]	93	1		T333	1		T334	1		T280	23
auto[2]	59	1		T282	2		T167	12		T335	1
auto[3]	186	1		T27	1		T28	1		T221	1

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7474	1		T4	100		T23	4		T34	4
evic_idx[1]	7468	1		T4	100		T23	4		T34	4
evic_idx[2]	7465	1		T4	100		T23	4		T34	4
evic_idx[3]	7464	1		T4	100		T23	4		T34	4

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	28937	1		T4	400		T61	184		T104	160
evic_op[2]	337	1		T34	4		T27	1		T28	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	1	31	96.88	1

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[3]]	[evic_op[2]]	[auto[1]]	0	1	1

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7170	1		T4	100		T61	46		T104	40
evic_idx[0]	evic_op[1]	auto[1]	25	1		T280	6		T336	2		T337	2
evic_idx[0]	evic_op[1]	auto[2]	4	1		T338	3		T339	1		-	-
evic_idx[0]	evic_op[1]	auto[3]	42	1		T161	1		T340	4		T133	2
evic_idx[0]	evic_op[2]	auto[0]	68	1		T34	1		T227	8		T69	2
evic_idx[0]	evic_op[2]	auto[1]	3	1		T333	1		T335	1		T341	1
evic_idx[0]	evic_op[2]	auto[2]	1	1		T342	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[3]	11	1		T221	1		T284	1		T343	1
evic_idx[1]	evic_op[1]	auto[0]	7171	1		T4	100		T61	46		T104	40
evic_idx[1]	evic_op[1]	auto[1]	23	1		T280	7		T336	3		T337	2
evic_idx[1]	evic_op[1]	auto[2]	8	1		T344	1		T345	1		T338	4
evic_idx[1]	evic_op[1]	auto[3]	34	1		T161	1		T340	1		T133	3
evic_idx[1]	evic_op[2]	auto[0]	67	1		T34	1		T227	8		T69	2
evic_idx[1]	evic_op[2]	auto[1]	2	1		T334	1		T346	1		-	-
evic_idx[1]	evic_op[2]	auto[2]	2	1		T282	1		T347	1		-	-
evic_idx[1]	evic_op[2]	auto[3]	12	1		T28	1		T282	1		T348	1
evic_idx[2]	evic_op[1]	auto[0]	7173	1		T4	100		T61	46		T104	40
evic_idx[2]	evic_op[1]	auto[1]	16	1		T280	5		T336	1		T337	2
evic_idx[2]	evic_op[1]	auto[2]	6	1		T344	1		T349	1		T345	1
evic_idx[2]	evic_op[1]	auto[3]	32	1		T161	2		T340	2		T133	4
evic_idx[2]	evic_op[2]	auto[0]	71	1		T34	1		T227	8		T69	2
evic_idx[2]	evic_op[2]	auto[1]	3	1		T350	1		T351	1		T352	1
evic_idx[2]	evic_op[2]	auto[2]	4	1		T282	1		T335	1		T353	1
evic_idx[2]	evic_op[2]	auto[3]	11	1		T27	1		T40	1		T41	1
evic_idx[3]	evic_op[1]	auto[0]	7170	1		T4	100		T61	46		T104	40
evic_idx[3]	evic_op[1]	auto[1]	21	1		T280	5		T336	3		T337	1
evic_idx[3]	evic_op[1]	auto[2]	7	1		T337	1		T349	1		T345	1
evic_idx[3]	evic_op[1]	auto[3]	35	1		T161	1		T340	1		T133	7
evic_idx[3]	evic_op[2]	auto[0]	70	1		T34	1		T227	8		T69	2
evic_idx[3]	evic_op[2]	auto[2]	3	1		T347	1		T353	1		T354	1
evic_idx[3]	evic_op[2]	auto[3]	9	1		T355	1		T356	1		T357	1