Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	25791	1		T96	15676		T322	2866		T323	2465
rd_lvl[2]	57808	1		T96	11759		T322	1198		T323	1400
rd_lvl[3]	17553	1		T324	895		T322	393		T325	834
rd_lvl[4]	29249	1		T324	263		T322	349		T326	2785
rd_lvl[5]	17009	1		T29	847		T39	631		T324	2
rd_lvl[6]	13963	1		T29	2587		T39	243		T225	376
rd_lvl[7]	7922	1		T29	1004		T39	18		T225	254
rd_lvl[8]	15799	1		T39	20		T225	18		T327	1396
rd_lvl[9]	4425	1		T225	4		T313	552		T327	101
rd_lvl[10]	6876	1		T225	4		T313	1188		T328	1344
rd_lvl[11]	3393	1		T39	20		T328	339		T327	1
rd_lvl[12]	5758	1		T329	1261		T330	526		T331	57
rd_lvl[13]	1983	1		T38	410		T329	313		T324	73
rd_lvl[14]	3501	1		T36	1343		T37	211		T38	455
rd_lvl[15]	3463	1		T36	288		T37	269		T332	383