Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	317299	1		T1	2		T3	2		T4	2
all_pins[1]	317299	1		T1	2		T3	2		T4	2
all_pins[2]	317299	1		T1	2		T3	2		T4	2
all_pins[3]	317299	1		T1	2		T3	2		T4	2
all_pins[4]	317299	1		T1	2		T3	2		T4	2
all_pins[5]	317299	1		T1	2		T3	2		T4	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1569652	1		T1	12		T3	12		T4	12
values[0x1]	334142	1		T29	6081		T39	1317		T36	3262
transitions[0x0=>0x1]	290986	1		T29	5032		T39	1228		T36	3262
transitions[0x1=>0x0]	290966	1		T29	5032		T39	1228		T36	3262

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	317126	1		T1	2		T3	2		T4	2
all_pins[0]	values[0x1]	173	1		T263	1		T264	1		T265	5
all_pins[0]	transitions[0x0=>0x1]	80	1		T263	1		T265	2		T318	1
all_pins[0]	transitions[0x1=>0x0]	79	1		T263	2		T264	6		T265	1
all_pins[1]	values[0x0]	317127	1		T1	2		T3	2		T4	2
all_pins[1]	values[0x1]	172	1		T263	2		T264	7		T265	4
all_pins[1]	transitions[0x0=>0x1]	133	1		T263	2		T264	6		T265	4
all_pins[1]	transitions[0x1=>0x0]	5002	1		T37	29		T332	541		T358	1069
all_pins[2]	values[0x0]	312258	1		T1	2		T3	2		T4	2
all_pins[2]	values[0x1]	5041	1		T37	29		T332	541		T358	1069
all_pins[2]	transitions[0x0=>0x1]	48	1		T264	2		T316	2		T317	1
all_pins[2]	transitions[0x1=>0x0]	214785	1		T29	4438		T39	932		T36	1631
all_pins[3]	values[0x0]	97521	1		T1	2		T3	2		T4	2
all_pins[3]	values[0x1]	219778	1		T29	4438		T39	932		T36	1631
all_pins[3]	transitions[0x0=>0x1]	181798	1		T29	3389		T39	843		T36	1631
all_pins[3]	transitions[0x1=>0x0]	70939	1		T29	594		T39	296		T36	1631
all_pins[4]	values[0x0]	208380	1		T1	2		T3	2		T4	2
all_pins[4]	values[0x1]	108919	1		T29	1643		T39	385		T36	1631
all_pins[4]	transitions[0x0=>0x1]	108902	1		T29	1643		T39	385		T36	1631
all_pins[4]	transitions[0x1=>0x0]	42	1		T265	2		T317	2		T319	2
all_pins[5]	values[0x0]	317240	1		T1	2		T3	2		T4	2
all_pins[5]	values[0x1]	59	1		T264	2		T265	2		T317	2
all_pins[5]	transitions[0x0=>0x1]	25	1		T264	2		T265	1		T319	1
all_pins[5]	transitions[0x1=>0x0]	119	1		T263	1		T264	1		T265	3