Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
293 |
1 |
|
T263 |
7 |
|
T264 |
7 |
|
T265 |
7 |
all_values[1] |
293 |
1 |
|
T263 |
7 |
|
T264 |
7 |
|
T265 |
7 |
all_values[2] |
293 |
1 |
|
T263 |
7 |
|
T264 |
7 |
|
T265 |
7 |
all_values[3] |
293 |
1 |
|
T263 |
7 |
|
T264 |
7 |
|
T265 |
7 |
all_values[4] |
293 |
1 |
|
T263 |
7 |
|
T264 |
7 |
|
T265 |
7 |
all_values[5] |
293 |
1 |
|
T263 |
7 |
|
T264 |
7 |
|
T265 |
7 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
914 |
1 |
|
T263 |
28 |
|
T264 |
22 |
|
T265 |
24 |
auto[1] |
844 |
1 |
|
T263 |
14 |
|
T264 |
20 |
|
T265 |
18 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
562 |
1 |
|
T263 |
19 |
|
T264 |
12 |
|
T265 |
11 |
auto[1] |
1196 |
1 |
|
T263 |
23 |
|
T264 |
30 |
|
T265 |
31 |
Summary for Variable cp_intr_test
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_test
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1033 |
1 |
|
T263 |
24 |
|
T264 |
24 |
|
T265 |
21 |
auto[1] |
725 |
1 |
|
T263 |
18 |
|
T264 |
18 |
|
T265 |
21 |
Summary for Cross intr_test_cg_cc
Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
36 |
8 |
28 |
77.78 |
8 |
Automatically Generated Cross Bins |
36 |
8 |
28 |
77.78 |
8 |
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for intr_test_cg_cc
Element holes
cp_intr | cp_intr_test | cp_intr_en | cp_intr_state | COUNT | AT LEAST | NUMBER |
[all_values[0] , all_values[1]] |
[auto[0]] |
* |
[auto[0]] |
-- |
-- |
4 |
[all_values[2] , all_values[3]] |
[auto[0]] |
* |
[auto[1]] |
-- |
-- |
4 |
Covered bins
cp_intr | cp_intr_test | cp_intr_en | cp_intr_state | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
auto[1] |
89 |
1 |
|
T263 |
2 |
|
T264 |
5 |
|
T265 |
2 |
all_values[0] |
auto[0] |
auto[1] |
auto[1] |
87 |
1 |
|
T265 |
3 |
|
T316 |
2 |
|
T317 |
2 |
all_values[0] |
auto[1] |
auto[0] |
auto[1] |
59 |
1 |
|
T263 |
4 |
|
T264 |
1 |
|
T265 |
1 |
all_values[0] |
auto[1] |
auto[1] |
auto[1] |
58 |
1 |
|
T263 |
1 |
|
T264 |
1 |
|
T265 |
1 |
all_values[1] |
auto[0] |
auto[0] |
auto[1] |
84 |
1 |
|
T263 |
2 |
|
T265 |
2 |
|
T316 |
3 |
all_values[1] |
auto[0] |
auto[1] |
auto[1] |
80 |
1 |
|
T264 |
4 |
|
T265 |
1 |
|
T318 |
1 |
all_values[1] |
auto[1] |
auto[0] |
auto[1] |
66 |
1 |
|
T263 |
3 |
|
T264 |
1 |
|
T265 |
1 |
all_values[1] |
auto[1] |
auto[1] |
auto[1] |
63 |
1 |
|
T263 |
2 |
|
T264 |
2 |
|
T265 |
3 |
all_values[2] |
auto[0] |
auto[0] |
auto[0] |
83 |
1 |
|
T263 |
4 |
|
T264 |
5 |
|
T265 |
3 |
all_values[2] |
auto[0] |
auto[1] |
auto[0] |
101 |
1 |
|
T263 |
2 |
|
T265 |
1 |
|
T318 |
3 |
all_values[2] |
auto[1] |
auto[0] |
auto[1] |
48 |
1 |
|
T264 |
1 |
|
T265 |
2 |
|
T317 |
1 |
all_values[2] |
auto[1] |
auto[1] |
auto[1] |
61 |
1 |
|
T263 |
1 |
|
T264 |
1 |
|
T265 |
1 |
all_values[3] |
auto[0] |
auto[0] |
auto[0] |
85 |
1 |
|
T263 |
2 |
|
T264 |
2 |
|
T265 |
2 |
all_values[3] |
auto[0] |
auto[1] |
auto[0] |
86 |
1 |
|
T263 |
1 |
|
T264 |
2 |
|
T265 |
1 |
all_values[3] |
auto[1] |
auto[0] |
auto[1] |
68 |
1 |
|
T263 |
2 |
|
T264 |
2 |
|
T265 |
4 |
all_values[3] |
auto[1] |
auto[1] |
auto[1] |
54 |
1 |
|
T263 |
2 |
|
T264 |
1 |
|
T318 |
2 |
all_values[4] |
auto[0] |
auto[0] |
auto[0] |
53 |
1 |
|
T263 |
5 |
|
T265 |
1 |
|
T318 |
1 |
all_values[4] |
auto[0] |
auto[0] |
auto[1] |
39 |
1 |
|
T264 |
1 |
|
T316 |
2 |
|
T319 |
1 |
all_values[4] |
auto[0] |
auto[1] |
auto[0] |
38 |
1 |
|
T264 |
1 |
|
T265 |
1 |
|
T319 |
3 |
all_values[4] |
auto[0] |
auto[1] |
auto[1] |
35 |
1 |
|
T263 |
1 |
|
T264 |
1 |
|
T265 |
2 |
all_values[4] |
auto[1] |
auto[0] |
auto[1] |
75 |
1 |
|
T264 |
2 |
|
T265 |
2 |
|
T316 |
5 |
all_values[4] |
auto[1] |
auto[1] |
auto[1] |
53 |
1 |
|
T263 |
1 |
|
T264 |
2 |
|
T265 |
1 |
all_values[5] |
auto[0] |
auto[0] |
auto[0] |
61 |
1 |
|
T263 |
2 |
|
T264 |
1 |
|
T265 |
1 |
all_values[5] |
auto[0] |
auto[0] |
auto[1] |
30 |
1 |
|
T318 |
1 |
|
T317 |
2 |
|
T320 |
2 |
all_values[5] |
auto[0] |
auto[1] |
auto[0] |
55 |
1 |
|
T263 |
3 |
|
T264 |
1 |
|
T265 |
1 |
all_values[5] |
auto[0] |
auto[1] |
auto[1] |
27 |
1 |
|
T264 |
1 |
|
T319 |
3 |
|
T321 |
1 |
all_values[5] |
auto[1] |
auto[0] |
auto[1] |
74 |
1 |
|
T263 |
2 |
|
T264 |
1 |
|
T265 |
3 |
all_values[5] |
auto[1] |
auto[1] |
auto[1] |
46 |
1 |
|
T264 |
3 |
|
T265 |
2 |
|
T319 |
1 |
User Defined Cross Bins for intr_test_cg_cc
Excluded/Illegal bins
NAME | COUNT | STATUS |
test_1_state_0 |
0 |
Illegal |